229Chapter 7 Interrupt/Exception Processing FunctionUser’s Manual U16580EE3V1UD007.3 Maskable InterruptsMaskable interrupt requests can be masked by interrupt control registers. The μPD70F3187 has106 maskable interrupt sources and the μPD70F3447 has 91 maskable interrupt sources.If two or more maskable interrupt requests are generated at the same time, they are acknowledgedaccording to the default priority. In addition to the default priority, eight levels of priorities can bespecified by using the interrupt control registers (programmable priority control).When an interrupt request has been acknowledged, the acknowledgement of other maskable interruptrequests is disabled and the interrupt disabled (DI) status is set.When the EI instruction is executed in an interrupt processing routine, the interrupt enabled (EI) statusis set, which enables servicing of interrupts having a higher priority than the interrupt request inprogress (specified by the interrupt control register). Note that only interrupts with a higher priority willhave this capability; interrupts with the same priority level cannot be nested.However, if multiple interrupts are executed, the following processing is necessary.(1) Save EIPC and EIPSW in memory or a general-purpose register before executing the EIinstruction.(2) Execute the DI instruction before executing the RETI instruction, then reset EIPC and EIPSW withthe values saved in (1).7.3.1 OperationIf a maskable interrupt occurs by INT input, the CPU performs the following processing, and transferscontrol to a handler routine:(1) Saves the restored PC to EIPC.(2) Saves the current PSW to EIPSW.(3) Writes an exception code to the lower half-word of ECR (EICC).(4) Sets the ID bit of the PSW and clears the EP bit.(5) Sets the handler address corresponding to each interrupt to the PC, and transfers control.The processing configuration of a maskable interrupt is shown in Figure 7-6.
