260Chapter 9 16-Bit Timer/Event Counter PUser’s Manual U16580EE3V1UD009.3 ConfigurationTMP includes the following hardware.Note: TIPm0 and TIPm1 captures inputs are shared with external trigger inputs TTRGPm, andexternal event inputs TEVTPm, and the corresponding TOPm0 and TOPm1 outputs.Remark: n = 0 to 8m = n for n= 0 to 7Figure 9-1: Block Diagram of Timer PNotes: 1. External pin is not available for TMP8.2. Internal signal inputs (INTTT0CC0 and INTTT0CC1 of TMT0, or INTCM10 and INTCM11 ofTMENC1) available on TMP8 only. (ref. to 9.4 (9) TMP input control register 2 (TPIC2)).Table 9-1: Configuration of TMP0 to TMP8Item ConfigurationTimer register 16-bit counterRegisters TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1)TMPn counter register (TPnCNT)CCR0 buffer register, CCR1 buffer registerTimer input 2 × 8 (TIPm0, TIPm1, TTRGPm, TEVTPm)NoteTimer output 2 × 8 (TOPm0, TOPm1)Note1 × 1 (TOP81)Control registers TMPn control registers 0, 1 (TPnCTL0, TPnCTL1)TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2)TMPn option registers 0, 1 (TPnOPT0, TPnOPT1)f /2XXf /4XXf /8XXf /16XXf /32XXf /64XXf /256XXf /1024XXSelectorInternal busInternal busTOPn0TOPn1TIPn0TIPn1SelectorEdgedetectorCCR0bufferregister CCR1bufferregisterTPnCCR0TPnCCR116-bit timer counterTPnCNTINTTPnOVINTTPnCC0INTTPnCC1OutputcontrollerClearNote 1Note 1Note 1EdgedetectorTEVTPnNote 1TTRGPnNote 1INTCM10Note 2INTT0CC0Note 2INTCM11Note 2INTT0CC1Note 2
