174Chapter 4 Bus Control Function (μPD70F3187 only)User’s Manual U16580EE3V1UD004.6 Wait Function4.6.1 Programmable wait function(1) Data wait control registers 0, 1 (DWC0, DWC1)To facilitate interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data waitstates with respect to the starting bus cycle for each CS area.The number of wait states can be specified by data wait control registers 0 and 1 (DWC0, DWC1)in programming. Just after system reset, all blocks have 7 data wait states inserted.These registers can be read/written in 16-bit units.Cautions: 1. The internal ROM area (flash memory) and the internal RAM area are not subjectto programmable waits and ordinarily no wait access is carried out. The internalperipheral I/O area is also not subject to programmable wait states, with waitcontrol performed only by each peripheral function.2. Write to the DWC0 and DWC1 registers after reset, and then do not change the setvalues. Also, do not access an external memory area other than that for thisinitialization routine until initial setting of the DWC0 and DWC1 registers isfinished. However, it is possible to access external memory areas whoseinitialization has been finished.Figure 4-8: Data Wait Control Registers 0, 1 (DWC0, DWC1) FormatRemark: n = 0 to 7After reset: 7777H R/W Address: FFFFF484H15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DWC0 0 DW 3 2 DW 31 DW 30 0 DW 22 DW 21 DW 20 0 DW 12 DW1 1 DW1 0 0 DW0 2 DW0 1 DW0 0CS3 CS2 CS1 CS0After reset: 7777H R/W Address: FFFFF486H15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DWC1 0 DW 7 2 DW 71 DW 70 0 DW 62 DW 61 DW 60 0 DW 52 DW5 1 DW5 0 0 DW4 2 DW4 1 DW4 0CS7 CS6 CS5 CS4DWCn2 DWCn1 DWCn0 Number of Inserted Data Wait StatesDuring CSn Area Access0 0 0 No wait states inserted0 0 1 10 1 0 20 1 1 31 0 0 41 0 1 51 1 0 61 1 1 7
