375Chapter 10 16-bit Inverter Timer/Counter RUser’s Manual U16580EE3V1UD00Figure 10-34: Examples when Peak Interrupts and Valley Interrupts Occur Alternately (2/2)(c) when TRnCMS = 1, TRnRDE = x (anytime rewrite)10.7.3 Interrupt thinning out function during counter saw tooth wave operationThe operations related to the interrupt thinning out function during counter saw tooth wave operation(PWM mode, PWM mode with dead time) are indicated below.• The interrupt subject to thinning out is INTTRnCD (peak interrupt). The saw tooth waveoperation occurs upon a match between the TRnCCR0 register and counter occurs.• TRnOPT1 register bit TRnICE is used to enable INTTRnCD interrupt output and to specifythinning out count targets.• The TRnOPT1 register bit TRnIOE setting is invalid. INTTRnOD interrupt output is prohibited.• TRnOPT1 register bit TRnRDE is used to specify reload thinning out Yes/No.• If thinning out Yes is specified, reload is executed at the same timing as interrupt outputfollowing thinning out.• If thinning out No is specified, reload is executed at the reload timing after write access to theTRnCCR1 register.Caution: When write access is performed to the TRnOPT1 register, the internal thinning outcounter is cleared when the register value is updated. Therefore, the interruptinterval may temporarily become longer than expected.To prevent this, it is recommended to set TRnCSM = 0 and TRnRDE = 1, and tochange the interrupt thinning out count with the reloaded setting according tointerrupt thinning out. Using this method, the interrupt interval is kept the same asthe setting value.CounterINTTRnCDINTTRnODTRnIDS4 to 0TRnID4 to 0Instantly reflectedInterrupt thinningout counterClear* Instantly reflected after rewrite. The reload timing is ignored.* The clear timing is transfer to the buffer, not register rewrite.00 01 02020400 01 02 03 04 00 0102000400 01 02 03 04
