193User’s Manual U16580EE3V1UD00Chapter 6 DMA Functions (DMA Controller)6.1 FeaturesThe V850E/PH2 includes a direct memory access (DMA) controller (DMAC) that executes and controlsDMA transfer.The DMAC controls data transfer between internal RAM (iRAM) and peripheral I/O registers, based onDMA requests issued by the on-chip peripheral I/O (A/D converters, inverter timers, and serialinterfaces), with the following features.• 2 channels for DMA transfer from A/D converter (ADC0, ADC1)- Transfer object: I/O → iRAM- Transfer size: 16 bits- Dedicated transfer channels for ADC0 and ADC1• 2 channels for DMA transfer to PWM timer (TMR0, TMR1)- Transfer object: iRAM → I/O- Transfer size: 16 bits- Dedicated transfer channels for TMR0 and TMR1• 2 channels for DMA transfer from serial interfaces on reception completion- Transfer object: I/O → iRAM- Transfer size: 8 or 16 bits- DMA request for each channel selectableClocked serial interfaces: CSIB0, CSIB1, CSI30, CSI31Asynchronous serial interface: UARTC0, UARTC1• 2 channels for DMA transfer to serial interfaces on transmission repetition- Transfer object: iRAM → I/O- Transfer size: 8 or 16 bits- DMA request for each channel selectableClocked serial interfaces: CSIB0, CSIB1, CS30, CSI31Asynchronous serial interface: UARTC0, UARTC1• Up to 256 transfer counts for each channel.
