147Chapter 4 Bus Control Function (μPD70F3187 only)User’s Manual U16580EE3V1UD004.3.1 Chip select control functionThe 64 MB memory area can be divided into 2 MB, 4 MB and 8 MB memory blocks by the chip areaselection control registers 0 and 1 (CSC0, CSC1) to control the chip select signals.The memory area can be effectively used by dividing the memory area into memory blocks using thechip select control function. The priority order is described below.(1) Chip area selection control registers 0, 1 (CSC0, CSC1)These registers can be read/written in 16-bit units. Valid by setting each bit (to 1). If different chiparea select signals are set to the same block, the priority order is controlled as follows.CSC0: Peripheral I/O area > CS0 > CS2 > CS1 > CS3 NoteCSC1: Peripheral I/O area > CS7 > CS5 > CS6 > CS4 NoteNote: Not all the chip area select signals are externally available on output pins. Even so, enablingchip area select signals other than CS0, CS1, CS3 or CS4, the setting for the correspondingmemory blocks will be effective too, regardless of an external chip select output pin.Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2)After reset: 2C11H R/W Address: FFFFF060H15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CSC0 CS 33 CS 32 CS 31 CS 30 CS 23 C S 22 C S 21 C S 20 C S 13 C S 12 C S 11 C S 10 C S 0 3 C S 0 2 C S 0 1 C S 0 0CS3 CS2 CS1 CS0After reset: 2C11H R/W Address: FFFFF062H15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0CSC1 CS 43 CS 42 CS 41 CS 40 CS 53 C S 52 C S 51 C S 50 C S 63 C S 62 C S 61 C S 60 C S 7 3 C S 7 2 C S 7 1 C S 7 0CS4 CS5 CS6 CS7
