179Chapter 4 Bus Control Function (μPD70F3187 only)User’s Manual U16580EE3V1UD004.8 Bus Priority OrderThere are two external bus cycles: operand data access and instruction fetch.As for the priority order, the highest priority has the instruction fetch than operand data access.An instruction fetch may be inserted between read access and write access during read modify writeaccess.Also, an instruction fetch may be inserted between bus access and bus access during CPU bus clock.Table 4-2: Bus Priority OrderPriorityOrderExternal Bus Cycle Bus MasterLowHighOperand data access CPUInstruction fetch CPU
