18 www.xilinx.com ML505/ML506/ML507 Evaluation PlatformUG347 (v3.1.1) October 7, 2009Chapter 1: ML505/ML506/ML507 Evaluation Platform RDigitally Controlled ImpedanceSome FPGA banks can support the digitally controlled impedance (DCI) feature inVirtex-5 FPGAs. Support for DCI is summarized in Table 1-2.2. DDR2 SODIMMThe ML50x platform is shipped with a single-rank unregistered 256 MB SODIMM. TheDDR2 SODIMM used is generally a Micron MT4HTF3264HY-53E or similar module. SerialPresence Detect (SPD) using an IIC interface to the DDR DIMM is also supported with theFPGA.Note: The board is only tested for DDR2 SDRAM operation at a 400 MHz data rate. Faster datarates might be possible but are not tested.MIG ComplianceThe ML50x DDR2 interface is MIG pinout compliant. The MIG DDR2 routing guidelinesoutlined in the Xilinx Memory Interface Generator (MIG) User Guide [Ref 17] have beenachieved.The board’s DDR2 SODIMM memory interface is designed to the requirements defined bythe MIG User Guide using the MIG tool. The MIG documentation requires that designersfollow the MIG pinout and layout guidelines. The MIG tool generates and ensures that theproper FPGA I/O pin selections are made in support of the board’s DDR2 interface. Theinitial pin selection for the board was modified and then re-verified to meet the MIGpinout requirements. To ensure a robust interface, the ML50x DDR2 layout incorporatesmatched trace lengths for data signals to the corresponding data strobe signal as defined inthe MIG user guide. See Appendix C, “References” for links to additional informationabout MIG and Virtex-5 FPGAs in general.Table 1-2: DCI Capability of FPGA BankFPGA Bank DCI Capability1 Not supported2 Not supported3 Not supported4 Not supported11 Yes, 49.9Ω resistors are installed12 Not supported13 Yes, 49.9Ω resistors are installed14 Yes, 49.9Ω resistors are installed15 Yes, 49.9Ω resistors are installed16 Yes, 49.9Ω resistors are installed17 Yes, 49.9Ω resistors are installed18 Not supported21 Yes, 49.9Ω resistors are installed