Xilinx ML505 User Manual

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Xilinx ML505 User Manual Manual pdf 28 page image

28 www.xilinx.com ML505/ML506/ML507 Evaluation PlatformUG347 (v3.1.1) October 7, 2009Chapter 1: ML505/ML506/ML507 Evaluation Platform RThe DVI connector (Table 1-14) supports the IIC protocol to allow the board to read themonitor’s configuration parameters. These parameters can be read by the FPGA using theVGA IIC bus.16. PS/2 Mouse and Keyboard PortsThe board contains two PS/2 ports: one for a mouse (P5) and the other for a keyboard (P4).Bidirectional level shifting transistors allow the FPGA's 1.8V I/O to interface with the 5VI/O of the PS/2 ports. The PS/2 ports on the board are powered directly by the main 5Vpower jack, which also powers the rest of the board.Caution! Care must be taken to ensure that the power load of any attached PS/2 devices doesnot overload the AC adapter.17. System ACE and CompactFlash ConnectorThe Xilinx System ACE CompactFlash (CF) configuration controller allows a Type ICompactFlash card to program the FPGA through the JTAG port. Both hardware andsoftware data can be downloaded through the JTAG port. The System ACE controllersupports up to eight configuration images on a single CompactFlash card. Theconfiguration address switches allow the user to choose which of the eight configurationimages to use.Table 1-14: DVI Controller ConnectionsNet Name FPGA PinDVI_D[0] AB8DVI_D[1] AC8DVI_D[2] AN12DVI_D[3] AP12DVI_D[4] AA9DVI_D[5] AA8DVI_D[6] AM13DVI_D[7] AN13DVI_D[8] AA10DVI_D[9] AB10DVI_D[10] AP14DVI_D[11] AN14DVI_XCLK_P AL11DVI_XCLK_N AL10DVI_HSYNC AM12DVI_VSYNC AM11DVI_DE AE8DVI_RESET_B AK6