Xilinx ML505 User Manual

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Xilinx ML505 User Manual Manual pdf 23 page image

ML505/ML506/ML507 Evaluation Platform www.xilinx.com 23UG347 (v3.1.1) October 7, 2009Detailed DescriptionRSingle-Ended Expansion I/O ConnectorsHeader J6 contains 32 single-ended signal connections to the FPGA I/Os. This permits thesignals on this connector to carry high-speed, single-ended data. All single-ended signalson connector J6 are matched length traces. The V CCIO of these signals can be set to 2.5V or3.3V by setting jumper J20. Table 1-10 summarizes the single-ended connections on thisexpansion I/O connector.Table 1-9: Expansion I/O Differential Connections (J4)J4 Differential Pin Pair Schematic Net Name FPGA PinPos Neg Pos Neg Pos Neg4 2 HDR2_4 HDR2_2 L34 K348 6 HDR2_8 HDR2_6 K33 K3212 10 HDR2_12 HDR2_10 P32 N3216 14 HDR2_16 HDR2_14 T33 R3420 18 HDR2_20 HDR2_18 R33 R3224 22 HDR2_24 HDR2_22 U33 T3428 26 HDR2_28 HDR2_26 U32 U3132 30 HDR2_32 HDR2_30 V32 V3336 34 HDR2_36 HDR2_34 W34 V3440 38 HDR2_40 HDR2_38 Y33 AA3344 42 HDR2_44 HDR2_42 AF34 AE3448 46 HDR2_48 HDR2_46 AF33 AE3352 50 HDR2_52 HDR2_50 AC34 AD3456 54 HDR2_56 HDR2_54 AC32 AB3260 58 HDR2_60 HDR2_58 AC33 AB3364 62 HDR2_64 HDR2_62 AN32 AP32Table 1-10: Expansion I/O Single-Ended Connections (J6)J6 Pin Schematic Net Name FPGA Pin2 HDR1_2 H334 HDR1_4 F346 HDR1_6 H348 HDR1_8 G3310 HDR1_10 G3212 HDR1_12 H3214 HDR1_14 J3216 HDR1_16 J34