Xilinx ML505 User Manual

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Xilinx ML505 User Manual Manual pdf 47 page image

ML505/ML506/ML507 Evaluation Platform www.xilinx.com 47UG347 (v3.1.1) October 7, 2009Detailed DescriptionRThe native output of the ICS843001-21 is LVPECL, so a resistor network is present tochange the voltage swing to LVDS levels. The LVDS output is then multiplexed outthrough Series AC coupling capacitors to allow the clock input of the FPGA to set thecommon mode voltage.SATA GTP/GTX Transceiver Clock GenerationAn Integrated Circuit Systems ICS844051-1 chip generates a high-quality, low-jitter,75-MHz or 150-MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clockis sent to the GTP/GTX transceiver driving the SATA connectors. Jumper J56 sets theSATA GTP/GTX transceiver clock frequency (see Table 1-32). Series AC couplingcapacitors are also present to allow the clock input of the FPGA to set the common modevoltage.SGMII / Loopback GTP/GTX Transceiver Clock GenerationAn Integrated Circuit Systems ICS844021I chip generates a high-quality, low-jitter,125-MHz LVDS clock from an inexpensive 25-MHz crystal oscillator. This clock is sent tothe GTPs driving the SGMII or onboard loopback interfaces. Series AC coupling capacitorsare also present to allow the clock input of the FPGA to set the common mode voltage.Table 1-31: Configurations for Clock Source and Frequency OptionsDIP Switch SW6 [1:8] Value Input RefClock(MHz)M DividerValueN DividerValueV CO(MHz)OutputFrequency(MHz)ApplicationN0 N1 N2 M0 M1 M2 SEL1 SEL01 1 0 0 0 1 0 1 19.44 32 4 622.08 155.52 SONET0 1 1 0 0 1 0 1 19.44 32 8 622.08 77.76 SONET0 0 0 0 0 1 0 1 19.44 32 1 622.08 622.08 SONET1 0 0 0 0 1 0 1 19.44 32 2 622.08 311.04 SONET0 0 1 1 1 0 1 0 25 25 5 625 125 Gigabit Ethernet1 1 1 1 1 0 1 0 25 25 10 625 62.5 Gigabit Ethernet1 0 1 0 1 0 1 0 25 24 6 600 100 PCI Express1 1 0 0 1 0 1 0 25 24 4 600 150 (1) SATA0 1 1 0 1 0 1 0 25 24 8 600 75 SATA1 1 0 1 1 0 1 0 25 25 4 625 156.25 XAUI/SRIONotes:1. Factory default setting.2. A 1 equates to the DIP switch in the on position.3. For Fibre Channel support, see Answer Record 24918.Table 1-32: Configuration for SATA GTP/GTX Clock SignalsSATA Clock Signal Board ConnectionSATA Clock FrequencyJumper J56• Jumper Off = 75 MHz• Jumper On = 150 MHz