Xilinx ML505 User Manual
Also see for ML505: Quick startQuick startGetting Started Tutorial
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ML505/ML506/ML507 Evaluation Platform www.xilinx.com 41UG347 (v3.1.1) October 7, 2009Detailed DescriptionRCPU JTAG Header PinoutFigure 1-8 shows J12, the 16-pin header that can be used to debug the software operating inthe CPU with debug tools such as Parallel Cable IV or third party tools.CPU JTAG Connection to FPGAThe connections between the CPU JTAG header (J12) and the FPGA are shown inTable 1-22. These are attached to the PowerPC® 440 processor JTAG debug resourcesusing normal FPGA routing resources. The JTAG debug resources are not hard-wired toparticular pins and are available for attachment in the FPGA fabric, making it possible toroute these signals to the preferred FPGA pins.Figure 1-8: CPU JTAG Header (J12)121615UG347_07_111505GNDCPU_VSENSECPU_TRST_NCPU_HALT_NCPU_TMSCPU_TDOJ12CPU_TDICPU_TCKTable 1-22: CPU JTAG Connection to FPGAPin Name FPGA Pin (U1) Connector Pin (J12)CPU_TDO E7 1FPGA_SC0_B (CPU_TDI) AF21 3CPU_TRST_N V10 4CPU_TCK E6 7CPU_TMS U10 9PC4_HALT_B(CPU_HALT_N) W9 11 |
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