Xilinx ML505 User Manual
Also see for ML505: Quick startQuick startGetting Started Tutorial
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ML505/ML506/ML507 Evaluation Platform www.xilinx.com 49UG347 (v3.1.1) October 7, 2009Detailed DescriptionR45. System MonitorThe ML50x supports both the dedicated and the auxiliary analog inputs to the Virtex-5FPGA System Monitor block. The VP and VN pins shown in Table 1-34, page 50 are thededicated pins, whereas the VAUXP[x], VAUXN[x] represent the 16 user-selectableauxiliary analog input channels. The ML50x PCB layout for the VP and VN pins isdesigned using differential pairs and anti-alias filtering in close proximity to the FPGA asrecommended in the Virtex-5 FPGA System Monitor User Guide [Ref 14]. Please note that thecircuitry connected to the 16 AUX channels on the ML50x are connected in a non-optimalfashion as they are implemented without anti-alias filtering at the FPGA. This tradeoff wasB2 HDR1_6 H34B3 HDR1_8 G33B4 GND N/AB5 HDR1_14 J32B6 HDR1_16 J34B7 GND N/AB8 HDR1_18 L33B9 HDR1_20 M32B10 GND N/AB11 HDR1_26 AA34B12 HDR1_28 AD32B13 GND N/AB14 HDR1_34 W32B15 HDR1_36 AH34B16 GND N/AB17 HDR1_42 AH32B18 HDR1_44 AK34B19 GND N/AB20 HDR2_42_SM_14_N AE34B21 HDR2_44_SM_14_P AF34B22 GND N/AB23 HDR1_54 AL33B24 HDR1_56 AM33B25 GND N/AB26 HDR1_62 AN34B27 HDR1_64 AN33Table 1-33: Landing Pad Signals on XGI Header (Cont’d)Pad Number Header Pin FPGA Pin |
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