Xilinx ML505 User Manual
Also see for ML505: Quick startQuick startGetting Started Tutorial
                                                            | |
Contents
| 
ML505/ML506/ML507 Evaluation Platform www.xilinx.com 43UG347 (v3.1.1) October 7, 2009Detailed DescriptionR40. PCI Express InterfaceTable 1-25 shows the PCIe connector (P21) that provides single-lane access through theRocketIO transceivers to the Virtex-5 FPGA integrated Endpoint block for PCIe designs.See the Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express Designs [Ref 11] formore information.Table 1-25: PCIe Connection to FPGAPin Name FPGA Pin(U1)EdgeConnector Pin(P21)DescriptionPCIE_RX_N AF1 B15 Integrated Endpoint block receive pairPCIE_RX_P AE1 B14PCIE_TX_N AE2 A17 Integrated Endpoint block transmit pairPCIE_TX_P AD2 A16PCIE_CLK_N AF3 A14 Integrated Endpoint block differentialclock pair from PCIe edge connectorPCIE_CLK_P AF4 A13PCIE_PRSNT_B AF24 A1, B17 Integrated Endpoint block present signalPCIE_PERST_B - A11 Integrated Endpoint block reset signalavailable on CPLDPCIE_WAKE_B - B11 Integrated Endpoint block wake signalavailable on CPLDNotes:1. For ML505/ML506 platforms, access is through GTP0 of GTP_X0Y1.2. For ML507 platforms, access is through GTX0 of GTX_X0Y2. |
Related manuals for Xilinx ML505
manualsdatabase
Your AI-powered manual search engine