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NEC V850E/PH2 manuals

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V850E/PH2

Brand: NEC | Category: Microcontrollers
Table of contents
  1. Preface
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Chapter 1 Introduction
  11. Device Features
  12. Applications
  13. Pin Configuration (Top View)
  14. Function Blocks
  15. On-chip units
  16. Chapter 2 Pin Functions
  17. Pin Status
  18. Description of Pin Functions
  19. Pin I/O Circuits and Recommended Connection of Unused Pins
  20. Noise Suppression
  21. Chapter 3 CPU Functions
  22. CPU Register Set
  23. Program register set
  24. System register set
  25. Floating point arithmetic unit register set
  26. Operating Modes
  27. Operation mode specification
  28. Address Space
  29. Images
  30. Wrap-around of CPU address space
  31. Memory map
  32. Areas
  33. Peripheral I/O registers list
  34. Programmable peripheral I/O area
  35. Specific registers
  36. System wait control register (VSWC)
  37. Cautions
  38. Chapter 4 Bus Control Function (μPD70F3187 only)
  39. Memory Block Function
  40. Chip select control function
  41. Bus Cycle Type Control Function
  42. Bus cycle type configuration
  43. Bus Access
  44. Bus sizing function
  45. Endian control function
  46. Bus width
  47. Wait Function
  48. Idle State Insertion Function
  49. Bus Priority Order
  50. Boundary Operation Conditions
  51. Chapter 5 Memory Access Control Function (μPD70F3187 only)
  52. SRAM connection
  53. SRAM, external ROM, external I/O access
  54. Chapter 6 DMA Functions (DMA Controller)
  55. Control Registers
  56. DMA Channel Priorities
  57. DMA transfer of PWM timer reload (TMR0, TMR1)
  58. DMA transfer of serial interfaces
  59. Forcible termination of DMA transfer
  60. DMA Interrupt Function
  61. Chapter 7 Interrupt/Exception Processing Function
  62. Non-maskable Interrupt
  63. Operation
  64. Restore
  65. Non-maskable interrupt status flag (NP)
  66. Maskable Interrupts
  68. Priorities of maskable interrupts
  69. Interrupt control register (PICn)
  70. Interrupt mask registers 0 to 6 (IMR0 to IMR6)
  71. In-service priority register (ISPR)
  72. Maskable interrupt status flag (ID)
  73. Interrupt trigger mode selection
  74. Software Exception
  76. Exception status flag (EP)
  77. Exception Trap
  78. Periods in Which CPU Does Not Acknowledge Interrupts
  79. Chapter 8 Clock Generator
  80. Power Save Control
  81. HALT mode
  82. Chapter 9 16-Bit Timer/Event Counter P
  83. Configuration
  86. Interval timer mode (TPnMD2 to TPnMD0 = 000B)
  87. External event count mode (TPnMD2 to TPnMD0 = 001B)
  88. External trigger pulse output mode (TPnMD2 to TPnMD0 = 010B)
  89. One-shot pulse mode (TPnMD2 to TPnMD0 = 011B)
  90. PWM mode (TPnMD2 to TPnMD0 = 100B)
  91. Free-running mode (TPnMD2 to TPnMD0 = 101B)
  92. Pulse width measurement mode (TPnMD2 to TPnMD0 = 110B)
  93. Counter synchronous operation function
  94. Features
  97. Basic Operation
  98. Compare register rewrite operation
  99. List of outputs in each mode
  100. Match Interrupts
  101. Compare match interrupt related cautions
  102. Flags
  103. Normal phase/inverted phase simultaneous active detection flag
  104. Reload hold flag
  105. Interrupt Thinning Out Function
  106. Operation of interrupt thinning out function
  107. Operation examples when peak interrupts and valley interrupts occur alternately
  108. Interrupt thinning out function during counter saw tooth wave operation
  109. A/D Conversion Trigger Function
  110. A/D conversion trigger operation
  111. Error Interrupts
  112. Operation in Each Mode
  113. Chapter 10 16-bit Inverter Timer/Counter R
  114. External event count mode
  115. External trigger pulse output mode (TMR1 only)
  116. One-shot pulse mode
  117. PWM mode
  118. Free-running mode
  119. Pulse width measurement mode (TMR1 only)
  120. Triangular wave PWM mode
  121. High-accuracy T-PWM mode
  122. PWM mode with dead time
  127. Method for writing to compare register
  130. External trigger pulse output mode
  134. Pulse width measurement mode
  136. Encoder count function
  137. Offset trigger generation mode
  138. Timer (TMENC10) (μPD70F3187 only)
  139. Basic Configuration
  142. Operation in general-purpose timer mode
  143. Operation in UDC mode
  144. Supplementary Description of Internal Operation
  145. Clearing of count value upon occurrence of compare match
  146. Interrupt signal output upon compare match
  147. Chapter 13 Auxiliary Frequency Output Function (AFO)
  150. Chapter 14 A/D Converter
  154. Operation mode and trigger mode
  155. Operation in A/D Trigger Mode
  156. Scan mode operations
  157. Operation in Timer Trigger Mode
  158. Scan mode operation
  159. Operation in External Trigger Mode
  161. Precautions
  162. Chapter 15 Asynchronous Serial Interface C (UARTC)
  165. Interrupt Requests
  167. SBF transmission/reception format
  168. SBF transmit operation
  169. SBF receive operation
  170. UART transmit operation
  171. Continuous transmit operation
  172. UART receive operation
  173. Receive error
  174. Parity types and operations
  175. Receive data noise filter
  176. Dedicated Baud Rate Generator
  177. Baud rate
  178. Baud rate setting example
  179. Allowable baud rate range during reception
  180. Baud rate during continuous transmission
  184. Single transfer mode (master mode, transmission mode)
  185. Single transfer mode (master mode, reception mode)
  186. Continuous mode (master mode, transmission/reception mode)
  187. Continuous mode (master mode, transmission mode)
  188. Continuous mode (master mode, reception mode)
  189. Continuous reception mode (error)
  190. Continuous mode (slave mode, transmission/reception mode)
  191. Continuous mode (slave mode, reception mode)
  192. Clock timing
  193. Output Pins
  194. Operation Flow
  195. Baud Rate Generator
  197. Baud rate generation
  201. Dedicated Baud Rate Generator 3n (BRG3n)
  203. Function of CSI data buffer register (CSIBUFn)
  204. Data transfer direction specification function
  205. Transfer data length changing function
  206. Function to select serial clock and data phase
  207. Master mode
  208. Slave mode
  209. Transfer clock selection function
  210. Consecutive mode
  211. Transmission mode
  212. Delay control of transmission/reception completion interrupt (INTC3n)
  213. Transfer wait function
  215. CSIBUFn overflow interrupt signal (INTC3nOVF)
  216. Operating Procedures
  217. Single mode (master mode, reception mode)
  218. Single mode (master mode, transmission/reception mode)
  219. Single mode (slave mode, transmission mode)
  220. Single mode (slave mode, reception mode)
  221. Single mode (slave mode, transmission/reception mode)
  222. Consecutive mode (master mode, transmission mode)
  223. Consecutive mode (master mode, reception mode)
  224. Consecutive mode (master mode, transmission/reception mode)
  225. Consecutive mode (slave mode, transmission mode)
  226. Consecutive mode (slave mode, reception mode)
  227. Consecutive mode (in slave mode and transmission/reception mode)
  230. Overview of functions
  232. CAN Protocol
  233. Frame types
  234. Error frame
  235. Overload frame
  236. Functions
  237. Multi masters
  238. Baud rate control function
  239. Connection with Target System
  240. Internal Registers of CAN Controller
  241. CAN Controller configuration
  242. CAN registers overview
  243. Register bit configuration
  244. Bit Set/Clear Function
  246. CAN Controller Initialization
  247. Transition from Initialization Mode to Operation Mode
  248. Resetting error counter CnERC of CAN module
  249. Message Reception
  250. Receive history list function
  251. Mask function
  252. Multi buffer receive block function
  253. Remote frame reception
  254. Message Transmission
  255. Transmit history list function
  256. Automatic block transmission (ABT)
  257. Transmission abort process
  258. Remote frame transmission
  259. Power Saving Modes
  260. CAN stop mode
  261. Example of using power saving modes
  262. Interrupt Function
  263. Diagnosis Functions and Special Operational Modes
  264. Single-shot mode
  265. Receive/Transmit Operation in Each Operation Mode
  266. Time Stamp Function
  267. Baud Rate Settings
  268. Representative examples of baud rate settings
  269. Operation of CAN Controller
  273. Port Configuration
  274. Function of each port
  275. Port types
  276. Peripheral registers of I/O ports
  277. Peripheral registers of valid edge control
  278. Port Pin Functions
  279. Port 1
  280. Port 2
  281. Port 3
  282. Port 4
  283. Port 5
  284. Port 6
  285. Port 7
  286. Port 8
  287. Port 9
  288. Port 10
  289. Port AL
  290. Port AH
  291. Port DL
  292. Port DH
  293. Port CS
  294. Port CT
  295. Port CM
  296. Port CD
  297. Noise Elimination
  298. Chapter 21 Reset Function
  300. Chapter 22 Internal RAM Parity Check Function
  302. Chapter 23 On-Chip Debug Function (OCD)
  303. Connection with N-Wire Type Emulator
  305. Chapter 24 Flash Memory
  306. Memory Configuration
  307. Functional Outline
  308. Rewriting by Dedicated Flash Programmer
  309. Communication mode
  310. Flash memory control
  311. Selection of communication mode
  312. Communication commands
  313. Pin connection
  314. Rewriting by Self Programming
  316. Chapter 25 Electrical Specifications
  317. General Characteristics
  318. Oscillator characteristics
  319. DC Characteristics
  320. AC Characteristics
  321. External asynchronous memory access read timing
  322. External asynchronous memory access write timing
  323. Reset Timing (Power Up/Down Sequence)
  324. Interrupt timing
  325. Peripheral Characteristics
  326. Serial interface characteristics
  327. A/D Converter Characteristics
  328. Flash Programming Characteristics
  329. Chapter 26 Package Drawings
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