9-24 L60 LINE PHASE COMPARISON SYSTEM – INSTRUCTION MANUALOVERVIEW CHAPTER 9: THEORY OF OPERATION9The receiver output is now symmetrical, but can be phase-shifted in the lagging direction from the actual keying signal atthe remote terminal. This latter result is not good, but it can be mitigated. In addition, there is the propagation delay ingetting the communication signal from the remote transmitter to the local receiver (1 millisecond per 186 miles) plus thedelay in the receiver itself. All of these compound to produce a receiver output that can be significantly phase-delayedfrom the current at the remote end of the line.This is undesirable because it introduces an error in the phase comparison. There is no way to eliminate this phase delaybut there is a way to compensate for it. This compensation is accomplished by the phase delay timer in the comparer inputcircuit.9.1.7.2 Phase delay adjustmentThe phase delay adjustment is a timer that is set with a pickup and a drop-out delay that are equal to each other so that itintroduces a phase delay without affecting the symmetry of the input signal. Its output is the same shape as that of thesquaring amplifier but delayed in time by the setting. This time delay setting is made in the field to be just equal to the sumof the three delays (symmetry adjustment, propagation, and receiver) discussed earlier. Thus, with this arrangement in thescheme of the previous figure, an external fault produces an output from the symmetry adjustment logic exactly in phaseand symmetrical with the output of the phase delay logic. This is necessary for proper blocking. For internal faults, theoutput from the phase delay timer is symmetrical with, but 180 degrees out of phase with the receiver output. This isnecessary for tripping. Note that any errors in these adjustments can reduce the tripping margins for internal faults and/orreduce the blocking margins during external faults.Note that the setting of the phase delay timer depends on the channel operating time, and that the total tripping time ofthe scheme is affected by this timer setting. Thus, the tripping speed of the scheme depends to that degree on the channeloperating time.9.1.7.3 Transient blockingTransient blocking is a feature that is included in all phase comparison schemes. It adds to the security of the schemeduring and immediately after the clearing of external faults. The following figure is a representation of Figure 1-15 exceptwith the transient blocking logic added. This consists of AND3, AND4, and the (15-99)/(15-99) transient blocking timer.Figure 9-16: Blocking scheme with transient blocking logicThe logic of the transient blocking scheme is such that if a fault is detected (indicated by the operation of FDH) but no triptakes place (as indicated by no output from the trip integrator timer), then AND3 produces an output to the transientblocking timer (15-99)/(15-99). If this condition persists long enough for the transient blocking timer to produce an output,
