ML51Dec. 05, 2018 Page 184 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUAL11.3 Input Capture ModuleThe input capture module along with Timer 2 implements the input capture function. The input capturemodule is configured through CAPCON0~2 registers. The input capture module supports 3-channelinputs (CAP0, CAP1, and CAP2). Each input channel consists its own noise filter, which is enabled viasetting ENF0~2 (CAPCON2[6:4]). It filters input glitches smaller than four system clock cycles. Inputcapture channels has their own independent edge detector but share the unique Timer 2. Each triggeredge detector is selected individually by setting corresponding bits in CAPCON1. It supports positiveedge capture, negative edge capture, or any edge capture. Each input capture channel has to set itsown enabling bit CAPEN0~2 (CAPCON0[6:4]) before use.While input capture channel is enabled and the selected edge trigger occurs, the content of the freerunning Timer 2 counter, TH2 and TL2, will be captured, transferred, and stored into the captureregisters CnH and CnL. The edge triggering also causes CAPFn (CAPCON0.n) set by hardware. Theinterrupt will also generate if the ECAP (EIE0.2) and EA bit are both set. For three input capture flagsshare the same interrupt vector, user should check CAPFn to confirm which channel comes the inputcapture edge. These flags should be cleared by software.The bit CAPCR (CAPCON2.3) benefits the implement of period calculation. Setting CAPCR makes thehardware clear Timer 2 as 0000H automatically after the value of TH2 and TL2 have been capturedafter an input capture edge event occurs. It eliminates the routine software overhead of writing 16-bitcounter or an arithmetic subtraction.
