ML51Dec. 05, 2018 Page 352 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUAL28 POWER MANAGEMENTThe ML51 has several features that help user to control the power consumption of the device. Table27.4-1 Table 27.4-1 Power Mode Tablelists all power mode at ML51 series to save the powerconsumption. For a stable current consumption, the state and mode of each pin should be taken careof. The minimum power consumption can be attained by giving the pin state just the same as theexternal pulls for example output 1 if pull-high is used or output 0 if pull-low. If the I/O pin is floating,user is recommended to leave it as quasi-bidirectional mode.Table 27.4-1 Power Mode TableMode Clock Source CommentNormal mode Any clock source -Idle mode Any clock source Only CPU clock is stoped.Low power run mode Only for LIRC or LXT -Low power idle mode Only for LIRC or LXT Only CPU clock is stoped.Power-down mode (PD) Any clock source 1. CPU enters deep sleep mode2. Most clocks are disabled exceptACMP/LIRC/LXT, and only WDT/WKT peripheral clocks still enableif their clock sources are selected as LIRC/LXT.For each power mode, they have different entry setting and leaving condition. The Table 27.4-2 showsthe entry setting for each power mode. When chip power-on, chip is running in normal mode. User canenter each mode by setting IDL (PCON.0), LPR (PCON.5) and PD (PCON.1).Table 27.4-2 Entry setting of power down modeRegister/Instruction Mode LPR (PCON.5) PD (PCON.1) IDL (PCON.0)Normal mode 0 0 0Idle mode 0 0 1Low power run mode 1 0 0Low power idle mode 1 0 1Power-down mode X 1 XPCON – Power Control7 6 5 4 3 2 1 0SMOD SMOD0 LPR POF GF1 GF0 PD IDLR/W R/W RW R/W R/W R/W R/W R/WAddress: 87H, All pagess POR reset value: 0001 000b, other reset value: 000U 0000bBit Name Description
