ML51Dec. 05, 2018 Page 240 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUAL17.3 Operating Modes17.3.1 Master ModeThe SPI can operate in Master mode while MSTR (SPInCR.4) is set as 1. Only one Master SPI devicecan initiate transmissions. A transmission always begins by Master through writing to SPInDR. Thebyte written to SPInDR begins shifting out on MOSI pin under the control of SPCLK. Simultaneously,another byte shifts in from the Slave on the MISO pin. After 8-bit data transfer complete, SPIF(SPInSR.7) will automatically set via hardware to indicate one byte data transfer complete. At thesame time, the data received from the Slave is also transferred in SPInDR. User can clear SPIF andread data out of SPInDR.17.3.2 Slave ModeWhen MSTR is 0, the SPI operates in Slave mode. The SPCLK pin becomes input and it will beclocked by another Master SPI device. The SS̅̅̅̅̅ pin also becomes input. The Master device cannotexchange data with the Slave device until the SS̅̅̅̅̅ pin of the Slave device is externally pulled low.Before data transmissions occurs, the SS̅̅̅̅̅ of the Slave device should be pulled and remain low untilthe transmission is complete. If SS̅̅̅̅̅ goes high, the SPI is forced into idle state. If the SS̅̅̅̅̅ is forced tohigh at the middle of transmission, the transmission will be aborted and the rest bits of the receivingshifter buffer will be high and goes into idle state.In Slave mode, data flows from the Master to the Slave on MOSI pin and flows from the Slave to theMaster on MISO pin. The data enters the shift register under the control of the SPCLK from the Masterdevice. After one byte is received in the shift register, it is immediately moved into the read data bufferand the SPIF bit is set. A read of the SPInDR is actually a read of the read data buffer. To prevent anoverrun and the loss of the byte that caused by the overrun, the Slave should read SPInDR out andthe first SPIF should be cleared before a second transfer of data from the Master device comes in theread data buffer.17.4 Clock Formats and Data TransferTo accommodate a wide variety of synchronous serial peripherals, the SPI has a clock polarity bitCPOL (SPInCR.3) and a clock phase bit CPHA (SPInCR.2). Figure 17.4-1 SPI Clock Formats showsthat CPOL and CPHA compose four different clock formats. The CPOL bit denotes the SPCLK linelevel in its idle state. The CPHA bit defines the edge on which the MOSI and MISO lines are sampled.The CPOL and CPHA should be identical for the Master and Slave devices on the same system. ToCommunicate in different data formats with one another will result undetermined result.
