ML51Dec. 05, 2018 Page 274 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUAL20 PULSE WIDTH MODULATED (PWM)The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It canused on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as asimple digital to analog converter output through a low pass filter circuit.The ML51 PWM is especially designed for motor control by providing three pairs, maximum 16-bitresolution of PWM output with programmable period and duty. The architecture makes user easy todrive the one-phase or three-phase brushless DC motor (BLDC), or three-phase AC induction motor.Each of six PWM can be configured as one of independent mode, complementary mode, orsynchronous mode. If the complementary mode is used, a programmable dead-time insertion isavailable to protect MOS turn-on simultaneously. The PWM waveform can be edge-aligned or center-aligned with variable interrupt points.20.1 Functional Description20.1.1 PWM GeneratorThe PWM generator is clocked by the system clock or Timer 1 overflow divided by a PWM clock pre-scalar selectable from 1/1~1/128. The PWM period is defined by effective 16-bit period registers,{PWMnPH, PWMnPL}. The period is the same for all PWM channels for they share the same 16-bitperiod counter. The duty of each PWM is determined independently by the value of duty registers{PWMnC0H, PWMnC0L}, {PWMnC1H, PWMnC1L}, {PWMnC2H, PWMnC2L}, {PWMnC3H,PWMnC3L}, {PWMnC4H, PWMnC4L}, and {PWMnC5H, PWMnC5L}. With six duty registers, six PWMoutput can be generated independently with different duty cycles. The interval and duty of PWM signalis generated by a 16-bit counter comparing with the period and duty registers.To facilitate the three-phase motor control, a group mode can be used by setting GP (PWMnCON1.5),which makes {PWMnC0H, PWMnC0L} and {PWMnC1H, PWMnC1L} duty register decide duties of thePWM outputs. In a three-phase motor control application, two-group PWM outputs generally are giventhe same duty cycle. When the group mode is enabled, {PWMnC2H, PWMnC2L}, {PWMnC3H,PWMnC3L}, {PWMnC4H, PWMnC4L} and {PWMnC5H, PWMnC5L} registers have no effect. Thismean is {PWMnC2H, PWMnC2L} and {PWMnC4H, PWMnC4L} both as same as {PWMnC0H,PWMnC0L}. Also {PWMnC3H, PWMnC3L} and {PWMnC5H, PWMnC5L} are same as {PWMnC1H,PWMnC1L}.Note that enabling PWM does not configure the I/O pins into their output modeautomatically. User should configure I/O output mode via software manually.
