ML51Dec. 05, 2018 Page 321 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUAL25 TIMED ACCESS PROTECTION (TA)The ML51 has several features such as WDT and Brown-out detection that are crucial to properoperation of the system. If leaving these control registers unprotected, errant code may writeundetermined value into them and results in incorrect operation and loss of control. To prevent thisrisk, the ML51 has a protection scheme, which limits the write access to critical SFR. This protectionscheme is implemented using a timed access (TA). The following registers are related to the TAprocess.TA – Timed Access7 6 5 4 3 2 1 0TA[7:0]WAddress: C7H, All pages Reset value: 0000 0000bBit Name Description7:0 TA[7:0] Timed accessThe timed access register controls the access to protected SFR. To access protected bits, usershould first write AAH to the TA and immediately followed by a write of 55H to TA. After these twosteps, a writing permission window is opened for 4 clock cycles during this period that user maywrite to protected SFR.In timed access method, the bits, which are protected, have a timed write enable window. A write issuccessful only if this window is active, otherwise the write will be discarded. When the software writesAAH to TA, a counter is started. This counter waits for 3 clock cycles looking for a write of 55H to TA.If the second write of 55H occurs within 3 clock cycles of the first write of AAH, then the timed accesswindow is opened. It remains open for 4 clock cycles during which user may write to the protected bits.After 4 clock cycles, this window automatically closes. Once the window closes, the procedure shouldbe repeated to write another protected bits. Not that the TA protected SFR are required timed accessfor writing but reading is not protected. User may read TA protected SFR without giving AAH and 55Hto TA register. The suggestion code for opening the timed access window is shown below.(CLR EA) ;if any interrupt is enabled, disable temporallyMOV TA,#0AAHMOV TA,#55H(Instruction that writes a TA protected register)(SETBEA) ;resume interrupts enabledAny enabled interrupt should be disabled during this procedure to avoid delay between these threewritings. If there is no interrupt enabled, the CLR EA and SETB EA instructions can be left out.
