ML51Dec. 05, 2018 Page 243 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUAL17.5 Slave Select Pin ConfigurationThe ML51 SPI gives a flexible SS̅̅̅̅̅ pin feature for different system requirements. When the SPIoperates as a Slave, SS̅̅̅̅̅ pin always rules as Slave select input. When the Master mode is enabled, SS̅̅̅̅̅has three different functions according to DISMODF (SPInSR.3) and SSOE (SPInCR.7). By default,DISMODF is 0. It means that the Mode Fault detection activates. SS̅̅̅̅̅ is configured as a input pin tocheck if the Mode Fault appears. On the contrary, if DISMODF is 1, Mode Fault is inactivated and theSSOE bit takes over to control the function of the SS̅̅̅̅̅ pin. While SSOE is 1, it means the Slave selectsignal will generate automatically to select a Slave device. The SS̅̅̅̅̅ as output pin of the Master usuallyconnects with the SS̅̅̅̅̅ input pin of the Slave device. The SS̅̅̅̅̅ output automatically goes low for eachtransmission when selecting external Slave device and goes high during each idle state to de-selectthe Slave device. While SSOE is 0 and DISMODF is 1, SS̅̅̅̅̅ is no more used by the SPI and reverts tobe a general purpose I/O pin.17.6 Mode Fault DetectionThe Mode Fault detection is useful in a system where more than one SPI devices might becomeMasters at the same time. It may induce data contention. When the SPI device is configured as aMaster and the SS̅̅̅̅̅ input line is configured for Mode Fault input depending on SPInCR0, a Mode Faulterror occurs once the SS̅̅̅̅̅ is pulled low by others. It indicates that some other SPI device is trying toaddress this Master as if it is a Slave. Instantly the MSTR and SPIEN control bits in the SPInCR arecleared via hardware to disable SPI, Mode Fault flag MODF (SPInSR.4) is set and an interrupt isgenerated if ESPI and EA are enabled.17.7 Write Collision ErrorThe SPI is signal buffered in the transfer direction and double buffered in the receiving and transmitdirection. New data for transmission cannot be written to the shift register until the previous transactionis complete. Write collision occurs while SPInDR be written more than once while a transfer was inprogress. SPInDR is double buffered in the transmit direction. Any writing to SPInDR cause data to bewritten directly into the SPI shift register. Once a write collision error is generated, WCOL (SPInSR.6)will be set as 1 via hardware to indicate a write collision. In this case, the current transferring datacontinues its transmission. However the new data that caused the collision will be lost. Although theSPI logic can detect write collisions in both Master and Slave modes, a write collision is normally aSlave error because a Slave has no indicator when a Master initiates a transfer. During the receivingof Slave, a write to SPInDR causes a write collision in Slave mode. WCOL flag needs to be cleared viasoftware.
