ML51Dec. 05, 2018 Page 323 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUAL26 INTERRUPT SYSTEM26.1 Interrupt OverviewThe purpose of the interrupt is to make the software deal with unscheduled or asynchronous events.The ML51 has a four-priority-level interrupt structure with 30 interrupt sources. Each of the interruptsources has an individual priority setting bits, interrupt vector and enable bit. In addition, the interruptscan be globally enabled or disabled. When an interrupt occurs, the CPU is expected to service theinterrupt. This service is specified as an Interrupt Service Routine (ISR). The ISR resides at apredetermined address as shown in Table 26.1-1 Interrupt Vectors. When the interrupt occurs ifenabled, the CPU will vector to the respective location depending on interrupt source, execute thecode at this location, stay in an interrupt service state until the ISR is done. Once an ISR has begun, itcan be interrupted only by a higher priority interrupt. The ISR should be terminated by a return frominterrupt instruction RETI. This instruction will force the CPU return to the instruction that would havebeen next when the interrupt occurred.Table 26.1-1 Interrupt VectorsSource VectorAddessVectorNumber Source VectorAddressVectorNumberReset 0000H - Serial port 1 interrupt 007BH 15External interrupt 0 0003H 0 Timer 3 overflow 0083H 16Timer 0 overflow 000BH 1 Self Wake-up Timer interrupt 008BH 17External interrupt 1 0013H 2 CPU Hard Fault Interrupt 0093H 18Timer 1 overflow 001BH 3 SMC0 Interrupt 009BH 19Serial port 0 interrupt 0023H 4 PDMA0 Interrupt 00A3H 20Timer 2 event 002BH 5 PDMA1 Interrupt 00ABH 21I2C0 status/timer-out interrupt 0033H 6 SPI1 Interrupt 00B3H 22Pin interrupt 003BH 7 ACMP Interrupt 00BBH 23Brown-out detection interrupt 0043H 8 I2C1 status/timer-out interrupt 00C3H 24SPI0 interrupt 004BH 9 PWM1 Interrupt 00CBH 25WDT interrupt 0053H 10 Fault Brake1 interrupt 00D3H 26ADC interrupt 005BH 11 SMC1 Interrupt 00DBH 27Input capture interrupt 0063H 12 PDMA2 Interrupt 00E3H 28
