ML51Dec. 05, 2018 Page 233 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUALFigure 17.1-2 shows a typical interconnection of SPI devices. The bus generally connects devicestogether through three signal wires, MOSI to MOSI, MISO to MISO, and SPCLK to SPCLK. TheMaster devices select the individual Slave devices by using four pins of a parallel port to control thefour SS̅̅̅̅ pins. MCU1 and MCU2 play either Master or Slave mode. The SS̅̅̅̅ should be configured asMaster Mode Fault detection to avoid multi-master conflict.SPI clockgeneratorMISO MISOMOSI MOSISPCLK SPCLKGNDSS SS7 6 5 4 3 2 1 0SPI shift register7 6 5 4 3 2 1 0SPI shift registerMaster MCU Slave MCU** SS configuration follows DISMODF and SSOE bits.Figure 17.1-3 SPI Single-Master, Single-Slave InterconnectionFigure 17.1-3 shows the simplest SPI system interconnection, single-master and signal-slave. Duringa transfer, the Master shifts data out to the Slave via MOSI line. While simultaneously, the Mastershifts data in from the Slave via MISO line. The two shift registers in the Master MCU and the SlaveMCU can be considered as one 16-bit circular shift register. Therefore, while a transfer data pushedfrom Master into Slave, the data in Slave will also be pulled in Master device respectively. The transfereffectively exchanges the data, which was in the SPI shift registers of the two MCUs.By default, SPI data is transferred MSB first. If the LSBFE (SPInCR.5) is set, SPI data shifts LSB first.This bit does not affect the position of the MSB and LSB in the data register. Note that all the followingdescription and figures are under the condition of LSBFE logic 0. MSB is transmitted and receivedfirst.There are three SPI registers to support its operations, including SPI control register (SPInCR), SPIstatus register (SPInSR), and SPI data register (SPInDR). These registers provide control, status, datastorage functions, and clock rate selection. The following registers relate to SPI function.
