ML51Dec. 05, 2018 Page 337 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUALexecuted. On execution of the RETI instruction, the processor pops the Stack and loads the PC withthe contents at the top of the stack. User should take care that the status of the stack. The processordoes not notice anything if the stack contents are modified and will proceed with execution from theaddress put back into PC. Note that a simple RET instruction would perform exactly the same processas a RETI instruction, but it would not inform the Interrupt controller that the interrupt service routine iscompleted. RET would leave the controller still thinking that the service routine is underway, makingfuture interrupts impossible.26.5 Interrupt LatencyThe response time for each interrupt source depends on several factors, such as the nature of theinterrupt and the instruction underway. Each interrupt flags are polled and priority decoded eachsystem clock cycle. If a request is active and all three previous conditions are met, then the hardwaregenerated LCALL is executed. This LCALL itself takes 4 clock cycles to be completed. Thus, there is aminimum reaction time of 5 clock cycles between the interrupt flag being set and the interrupt serviceroutine being executed.A longer response time should be anticipated if any of the three conditions are not met. If a higher orequal priority is being serviced, then the interrupt latency time obviously depends on the nature of theservice routine currently being executed. If the polling cycle is not the last clock cycle of the instructionbeing executed, then an additional delay is introduced. The maximum response time (if no otherinterrupt is currently being serviced or the new interrupt is of greater priority) occurs if the device isperforming a RETI, and then executes a longest 6-clock-cycle instruction as the next instruction. Fromthe time an interrupt source is activated (not detected), the longest reaction time is 16 clock cycles.This period includes 5 clock cycles to complete RETI, 6 clock cycles to complete the longestinstruction, 1 clock cycle to detect the interrupt, and 4 clock cycles to complete the hardware LCALL tothe interrupt vector location.Thus in a single-interrupt system the interrupt response time will always be more than 5 clock cyclesand not more than 16 clock cycles.26.6 External Interrupt PinsThe external interrupt INT0̅̅̅̅̅̅̅ and INT1̅̅̅̅̅̅̅ can be used as interrupt sources. They are selectable to beeither edge or level triggered depending on bits IT0 (TCON.0) and IT1 (TCON.2). The bits IE0(TCON.1) and IE1 (TCON.3) are the flags those are checked to generate the interrupt. In the edgetriggered mode, the INT0̅̅̅̅̅̅̅ or INT1̅̅̅̅̅̅̅ inputs are sampled every system clock cycle. If the sample is high inone cycle and low in the next, then a high to low transition is detected and the interrupts request flagIE0 or IE1 will be set. Since the external interrupts are sampled every system clock, they have to beheld high or low for at least one system clock cycle. The IE0 and IE1 are automatically cleared when
