ML51Dec. 05, 2018 Page 24 of 401 Rev 1.00ML51 SERIES TECHNICAL REFERENCE MANUAL4.1.2 ML51 Series Multi Function Pin DiagramQFN33 Package4.1.2.1Corresponding Part Number: ML51TC0AE / ML51TB9AEQFN33ML51TC0AEML51TB9AE33 VSS1234567816151413121110924232221201918172526272829303132Top transparent viewVSSINT0 / CLKO / TM0 / PWM0_CH0 / PWM1_BRAKE / P4.6VDDPWM0_BRAKE / TM2_EXT0 / PWM1_CH0 / SPI1_SS / P3.3CLKO / TM2_EXT1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2TM2_EXT2 / PWM1_CH2 / UART0_TXD / UART3_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1TM2_EXT0 / PWM1_CH3 / UART0_RXD / SPI1_MOSI / P3.0VREFINT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2PWM0_BRAKE / PWM1_CH4 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1PWM0_BRAKE / PWM1_CH5 / PWM0_CH5 / I2C1_SDA / UART2_RXD / ACMP0_N1 / ADC_CH5 / P2.0EADC0_ST / X32_IN / PWM0_CH0 / UART2_RXD / P5.5X32_OUT / PWM0_CH1 / UART2_TXD / P5.4nRESETP5.6 / PWM0_BRAKE / PWM0_CH1 / CLKOP0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / PWM0_CH2 / CLKO / PWM1_BRAKEP5.2 / UART0_RXD / I2C0_SDA / XT1_OUTP5.3 / UART0_TXD / I2C0_SCL / XT1_INP1.7 / UART0_RXDP1.6 / UART0_TXDP1.5 / I2C1_SDAP1.4 / I2C1_SCLP4.0 / UART2_RXD / I2C0_SDA / PWM1_CH5 / ACMP1_OP4.1 / UART2_TXD / I2C0_SCL / PWM1_CH4 / ACMP0_OP5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLKP5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DATFigure 4.1-10 Multi Function Pin Assignment of QFN-33 Package
