Xilinx ML50 Series User Manual Manual pdf 11 page image
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Xilinx ML50 Series User Manual

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Contents
  1. revision history
  2. Table Of Contents
  3. Table Of Contents
  4. Guide Contents
  5. Additional Support Resources
  6. Online Document
  7. Introduction
  8. Package Contents
  9. Block Diagram
  10. Detailed Description
  11. Virtex-5 FPGA
  12. Digitally Controlled Impedance
  13. DDR2 SODIMM
  14. Oscillator Sockets
  15. User and Error LEDs (Active-High)
  16. User Pushbuttons (Active-High)
  17. Single-Ended Expansion I/O Connectors
  18. Other Expansion I/O Connectors
  19. Stereo AC97 Audio Codec
  20. IIC Bus with 8-Kb EEPROM
  21. System ACE and CompactFlash Connector
  22. ZBT Synchronous SRAM
  23. USB Controller with Host and Peripheral Ports
  24. Xilinx XCF32P Platform Flash PROM Configuration Storage Device
  25. AC Adapter and Input Power Switch/Jack
  26. Configuration Address and Mode DIP Switches
  27. SPI Flash
  28. System Monitor
  29. Configuration Options
  30. Platform Flash PROM Configuration
  31. Overview
Xilinx ML50 Series User Manual Manual pdf 11 page image
ML501 Evaluation Platform www.xilinx.com 11UG226 (v1.3) November 10, 2008IntroductionRBlock DiagramFigure 1-1 shows a block diagram of the ML501 Evaluation Platform (board).Figure 1-1: Virtex-5 FPGA ML501 Evaluation Platform Block DiagramVirtex-5 LXFPGAUG226_03_083006GPIO(Button/LED/DIP Switch)PLL Clock GeneratorPlus User OscillatorSystem MonitorSMA(Differential In/Out Clocks)Dual PS/2FlashSyncSRAMPlatform FlashSPISystem ACEControllerCPLDMisc. Glue LogicSelectMapSPI CfgBPI Flash CfgSlave SerialJTAGJTAG JTAG JTAGMaster SerialXGI HeaderUSBController10/100/1000Ethernet PHYAC97Audio CODECBattery andFan HeaderCF PC4RS-232 XCVRVideo DAC16 X 32Character LCDIIC EEPROMRJ-45Line Out /HeadphoneDigital AudioMic In / Line InSerialPiezo/SpeakerHostPeripheralPeripheral16321632 3216PT Host 240W10A Switching RegulatorPT Host 230W6A Switching RegulatorPT Host 230W6A Switching RegulatorTPS744013A LDO5V Brick3A2.5VTo VCCAUXTPS744013A LDO2.5VTo FPGA I/OTo FPGA I/OTPS511003A LDO0.9VTo VTTVREFTPS511003A LDO0.9VTo VTT3.3V5V1.8VTo PROMTo DDR2 SO-DIMM1.0VTo FPGA CoreUser IIC BusDDR2SO-DIMMDVI-I Video OutTo USB and PS/2
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This manual is suitable for:
ML50 SeriesML501
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