Xilinx ML50 Series User Manual

ML501 Evaluation Platform www.xilinx.com 9UG226 (v1.3) November 10, 2008RChapter 1ML501 Evaluation PlatformIntroductionThe ML501 Evaluation Platform enables designers to investigate and experiment withfeatures of Virtex-5 LX FPGAs. This user guide describes features and operation of theML501 Evaluation Platform.Features• Virtex-5 XC5VLX50-1FFG676 FPGA• 64-bit DDR2 small outline DIMM (SODIMM), compatible with EDK supported IP andsoftware drivers• Programmable system clock generator chip• One differential clock input pair and differential clock output pair with SMAconnectors• 3.3V clock oscillator socket populated with a 100-MHz oscillator• General purpose DIP switches, LEDs, and pushbuttons• Expansion header with 32 single-ended I/O, 16 LVDS capable differential pairs,14 spare I/Os shared with buttons and LEDs, power, JTAG chain expansioncapability, and IIC bus expansion• Stereo AC97 audio codec with line-in, line-out, 50-mW headphone, microphone-injacks, and SPDIF digital audio jacks• RS-232 serial port• 16-character x 2-line LCD display• One 8-Kb IIC EEPROM• DVI video connector (VGA supported with included adapter)• PS/2 mouse and keyboard connectors• System ACE™ CompactFlash configuration controller with Type I CompactFlashconnector• ZBT synchronous SRAM, 9 Mb on 32-bit data bus with four parity bits• Intel P30 StrataFlash linear flash chips (32 MB)• Serial Peripheral Interface™ (SPI) Flash (2 MB)• 10/100/1000 tri-speed Ethernet PHY transceiver• USB interface chip with host and peripheral ports• Piezo audio transducer• Rechargeable lithium battery to hold FPGA encryption keys