Xilinx ML50 Series User Manual

ML501 Evaluation Platform www.xilinx.com 19UG226 (v1.3) November 10, 2008Detailed DescriptionR7. User and Error LEDs (Active-High)There are a total of 15 active-High LEDs directly controllable by the FPGA:• Eight green LEDs are general purpose LEDs arranged in a row• Five green LEDs are positioned next to the North-East-South-West-Center-orientedpushbuttons (only the center one is cited in Figure 1-2, page 12)• Two red LEDs are intended to be used for signaling error conditions, such as buserrors, but can be used for any other purposeSome LEDs are buffered through the CPLD to allow the LED signals to be used as higher-performance I/O by way of the XGI expansion connector. Table 1-6 summarizes the LEDdefinitions and connections.GPIO_DIP_SW6 U5GPIO_DIP_SW7 U7GPIO_DIP_SW8 T7Table 1-5: DIP Switch Connections (SW4) (Continued)SW4 FPGA PinTable 1-6: User and Error LED ConnectionsReferenceDesignator Label/Definition Color FPGA Pin BufferedDS20 LED North Green Y8 YesDS21 LED East Green Y18 YesDS22 LED South Green AA8 YesDS23 LED West Green AA18 YesDS24 LED Center Green T22 YesDS17 GPIO LED 0 Green E13 YesDS16 GPIO LED 1 Green D14 YesDS15 GPIO LED 2 Green E12 YesDS14 GPIO LED 3 Green F12 YesDS13 GPIO LED 4 Green D15 NoDS12 GPIO LED 5 Green E15 NoDS11 GPIO LED 6 Green E10 NoDS10 GPIO LED 7 Green E11 NoD56 Error 1 Red N4 NoD55 Error 2 Red P5 No