Xilinx ML50 Series User Manual

ML501 Evaluation Platform www.xilinx.com 5UG226 (v1.3) November 10, 2008RPrefaceAbout This GuideThe ML50x evaluation platforms enable designers to investigate and experiment withfeatures of Virtex®-5 FPGAs. This user guide describes the features and operation of theML501 Evaluation Platform.Guide ContentsThis manual contains the following chapters:• Chapter 1, “ML501 Evaluation Platform,” provides details on the board components• Appendix A, “Programming the IDT Clock Chip,” is a tutorial that steps throughprogramming the clock chip on the ML501 board• Appendix B, “References”Additional DocumentationThe following documents are also available for download athttp://www.xilinx.com/virtex5.• Virtex-5 FPGA Family OverviewThe features and product selection of the Virtex-5 FPGA family are outlined in thisoverview.• Virtex-5 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and Switching Characteristic specifications for theVirtex-5 FPGA family.• Virtex-5 FPGA User GuideThis user guide includes chapters on:♦ Clocking Resources♦ Clock Management Technology (CMT)♦ Phase-Locked Loops (PLLs)♦ Block RAM and FIFO memory♦ Configurable Logic Blocks (CLBs)♦ SelectIO™ Resources♦ I/O Logic Resources♦ Advanced I/O Logic Resources• Virtex-5 FPGA RocketIO GTP Transceiver User Guide