Xilinx ML50 Series User Manual

18 www.xilinx.com ML501 Evaluation PlatformUG226 (v1.3) November 10, 2008Chapter 1: ML501 Evaluation Platform R4. Oscillator SocketsThe board has one crystal oscillator socket (X1) wired for standard LVTTL-type oscillators.It connects to the FPGA clock pin as shown in Table 1-4. The X1 socket is populated with a100-MHz oscillator and is powered by the 3.3V supply.The board also provides an IDT5V9885 (U8) EEPROM programmable clock generatordevice. This device is used to generate a variety of clocks to the board peripherals andFPGA. The programmable clock generator provides the following factory default single-ended outputs:• 25 MHz to the Ethernet PHY (U13)• 24.5 MHz to the audio codec (U16)• 27 MHz to the USB controller (U18)• 33 MHz to the Xilinx System ACE CF (U2)• 33 MHz, 27 MHz, and a differential 200 MHz clock to the Xilinx FPGAIf users change the factory default configuration of the clock generator chip, the relatedreference design material might not work as designed. Instructions for returning theIDT5V9885 to the factory default configuration are provided in Appendix A,“Programming the IDT Clock Chip.”5. LCD Brightness and Contrast AdjustmentTurning potentiometer R87 adjusts the image contrast of the character LCD. Thepotentiometer should be turned with a screwdriver.6. DIP Switches (Active-High)Eight general-purpose (active-High) DIP switches are connected to the user I/O pins of theFPGA. Table 1-5 summarizes these connections.Table 1-4: Oscillator Socket ConnectionLabel Clock Name FPGA Pin DescriptionX1 USER_CLK AD8 100 MHz single-endedU8 CLK_33MHZ_FPGA AB12 33 MHz single-endedU8 CLK_27MHZ_FPGA AD13 27 MHz single-endedU8 CLK_DIFF_FPGA_P E16 200 MHz differential pair (pos)U8 CLK_DIFF_FPGA_N E17 200 MHz differential pair (neg)Table 1-5: DIP Switch Connections (SW4)SW4 FPGA PinGPIO_DIP_SW1 U4GPIO_DIP_SW2 V3GPIO_DIP_SW3 T4GPIO_DIP_SW4 T5GPIO_DIP_SW5 U6