Xilinx ML50 Series User Manual

14 www.xilinx.com ML501 Evaluation PlatformUG226 (v1.3) November 10, 2008Chapter 1: ML501 Evaluation Platform R1. Virtex-5 FPGAA Xilinx Virtex-5 FPGA, XC5VLX50-1FFG676, is installed on the Evaluation Platform (theboard).ConfigurationThe board supports configuration in all modes: JTAG, Master Serial, Slave Serial, MasterSelectMAP, Slave SelectMAP, Byte-wide Peripheral Interface (BPI) Up, BPI Down, and SPImodes. See the “Configuration Options,” page 36 section for more information.I/O Voltage RailsThe FPGA has 14 banks. The I/O voltage applied to each bank is summarized in Table 1-1.Table 1-1: I/O Voltage Rail of FPGA BanksFPGA Bank I/O Voltage Rail0 3.3V1 3.3V2 3.3V3 2.5V4 3.3V11 User selectable as 2.5V or 3.3V using jumper J2012 3.3V13 User selectable as 2.5V or 3.3V using jumper J2014 1.8V15 3.3V16 1.8V17 3.3V18 1.8V21 1.8V