Xilinx ML50 Series User Manual

16 www.xilinx.com ML501 Evaluation PlatformUG226 (v1.3) November 10, 2008Chapter 1: ML501 Evaluation Platform R2. DDR2 SODIMMThe ML501 platform is shipped with a single-rank unregistered 256 MB SODIMM. TheDDR2 SODIMM used is generally a Micron MT4HTF3264HY-53E or similar module. SerialPresence Detect (SPD) using an IIC interface to the DDR DIMM is also supported with theFPGA.Note: The board is only tested for DDR2 SDRAM operation at a 400 MHz data rate. Faster datarates might be possible but are not tested.MIG ComplianceThe ML50x DDR2 interface is MIG pinout compliant. The MIG DDR2 routing guidelinesoutlined in the Xilinx Memory Interface Generator (MIG) User Guide [Ref 13] have beenachieved.The board’s DDR2 SODIMM memory interface is designed to the requirements defined bythe MIG User Guide using the MIG tool. The MIG documentation requires that designersfollow the MIG pinout and layout guidelines. The MIG tool generates and ensures that theproper FPGA I/O pin selections are made in support of the board’s DDR2 interface. Theinitial pin selection for the board was modified and then re-verified to meet the MIGpinout requirements. To ensure a robust interface, the ML50x DDR2 layout incorporatesmatched trace lengths for data signals to the corresponding data strobe signal as defined inthe MIG user guide. See Appendix B, “References” for links to additional informationabout MIG and Virtex-5 FPGAs in general.DDR2 Memory ExpansionThe DDR2 interface support user installation of SODIMM modules with more memorysince higher order address and chip select signals are also routed from the SODIMM to theFPGA.DDR2 Clock SignalTwo matched length pairs of DDR2 clock signals are broadcast from the FPGA to theSODIMM. The FPGA design is responsible for driving both clock pairs with low skew. Thedelay on the clock trace is designed to match the delay of the other DDR2 control signals.DDR2 SignalingAll DDR2 SDRAM control signals are terminated through 47Ω resistors to a 0.9V VTTreference voltage. The FPGA DDR2 interface supports SSTL18 signaling and all DDR2signals are controlled impedance. The DDR2 data, mask, and strobe signals are matchedlength within byte groups. The ODT functionality of the SODIMM should be utilized.3. Differential Clock Input And Output With SMA ConnectorsHigh-precision clock signals can be input to the FPGA using differential clock signalsbrought in through 50Ω SMA connectors. This allows an external function generator orother clock source to drive the differential clock inputs that directly feed the global clockinput pins of the FPGA. The FPGA can be configured to present a 100Ω terminationimpedance.