Xilinx ML50 Series User Manual

6 www.xilinx.com ML501 Evaluation PlatformUG226 (v1.3) November 10, 2008Preface: About This Guide RThis guide describes the RocketIO™ GTP transceivers available in the Virtex-5 LXTand SXT platform devices.• Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller User GuideThis user guide describes the dedicated Tri-Mode Ethernet Media Access Controlleravailable in the Virtex-5 LXT and SXT platform devices.• Virtex-5 FPGA Integrated Endpoint Block User Guide for PCI Express® DesignsThis user guide describes the integrated Endpoint blocks in the Virtex-5 LXT and SXTplatform devices for PCI Express designs.• XtremeDSP Design ConsiderationsThis guide describes the XtremeDSP. slice and includes reference designs for using theDSP48E.• Virtex-5 FPGA Configuration User GuideThis all-encompassing configuration guide includes chapters on configurationinterfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAGconfiguration, reconfiguration techniques, and readback through the SelectMAP andJTAG interfaces.• Virtex-5 FPGA System Monitor User GuideThe System Monitor functionality available in all the Virtex-5 devices is outlined inthis guide.• Virtex-5 FPGA Packaging and Pinout SpecificationThis specification includes the tables for device/package combinations and maximumI/Os, pin definitions, pinout tables, pinout diagrams, mechanical drawings, andthermal specifications.Additional Support ResourcesTo search the database of silicon and software questions and answers, or to create atechnical support case in WebCase, see the Xilinx® website at:http://www.xilinx.com/support.Typographical ConventionsThis document uses the following typographical conventions. An example illustrates eachconvention.Convention Meaning or Use ExampleItalic fontReferences to other documents See the Virtex-5 ConfigurationGuide for more information.Emphasis in text The address (F) is asserted afterclock event 2.Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex5