Xilinx ML50 Series User Manual

28 www.xilinx.com ML501 Evaluation PlatformUG226 (v1.3) November 10, 2008Chapter 1: ML501 Evaluation Platform RNote: System ACE configuration is enabled by way of a DIP switch. See “31. Configuration Addressand Mode DIP Switches.”The board also features a System ACE failsafe mode. In this mode, if the System ACEcontroller detects a failed configuration attempt, it automatically reboots back to apredefined configuration image. The failsafe mode is enabled by inserting two jumpersacross J18 and J19 (in horizontal or vertical orientation).Caution! Use caution when inserting a CompactFlash card with exposed metallic surfaces.Improper insertion can cause a short with the traces or components on the board.The System ACE MPU port is connected to the FPGA. This connection allows the FPGA touse the System ACE controller to reconfigure the system or access the CompactFlash cardas a generic FAT file system. The data bus for the System ACE MPU port is shared with theUSB controller.18. ZBT Synchronous SRAMThe ZBT synchronous SRAM (ISSI IS61NLP25636A-200TQL) provides high-speed, low-latency external memory to the FPGA. The memory is organized as 256K x 36 bits. Thisorganization provides for a 32-bit data bus with support for four parity bits.Note: The SRAM and FLASH memory share the same data bus.19. Linear Flash ChipsA NOR linear flash device (Intel JS28F256P30T95) is installed on the board to provide32 MB of flash memory. This memory provides non-volatile storage of data, software, orbitstreams. The flash chip is 16 bits wide and shares its data bus with SRAM. The flashmemory can also be used to program the FPGA.Note: The reset for the AC97 Codec is shared with the reset signal for the flash memory chips andis designed to be asserted at power-on or at system reset.20. Xilinx XC95144XL CPLDA Xilinx XC95144XL CPLD provides general-purpose glue logic for the board. The CPLDis located under the removable LCD and is not visible in Figure 1-2. The CPLD isprogrammed from the main JTAG chain of the board. The CPLD is mainly used toimplement level translators, simple gates, and buffers.21. 10/100/1000 Tri-Speed Ethernet PHYThe ML501 Evaluation Platform contains a Marvell Alaska PHY device (88E1111)operating at 10/100/1000 Mb/s. The board supports MII, GMII, and RGMII interfacemodes with the FPGA. The PHY is connected to a Halo HFJ11-1G01E RJ-45 connector withbuilt-in magnetics. The PHY is configured to default at power-on or reset to the following