108 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User GuideUG334 (v1.1) June 19, 2008Chapter 13: DDR2 SDRAM RAll DDR2 SDRAM interface pins connect to the FPGA’s I/O Bank 3 on the FPGA. I/O Bank3 and the DDR2 SDRAM are both powered by 1.8V, supplied by a second NationalSemiconductor LP3906 regulator from the board’s 5V supply input. The 0.9V referencevoltage, common to the FPGA and DDR2 SDRAM, is also supplied by the NationalSemiconductor regulator. See “Voltage Regulators” in the Starter Kit Schematic.All DDR2 SDRAM interface signals are terminated. See “DDR2 SDRAM TerminationNetwork” in the Starter Kit Schematic for information on the SSTL18 termination schemeused on the board.DDR2 SDRAM ConnectionsTable 13-1 shows the connections between the FPGA and the DDR2 SDRAM. Also see“32Mx16 DDR2 SDRAM” in the Starter Kit Schematic.Table 13-1: FPGA-to-DDR2 SDRAM ConnectionsCategoryDDR2 SDRAMSignal NameFPGA PinNumber FunctionAddressSD_A15 W3 Unused on 512 Mbit DDR2 SDRAM devicebut provided for potential future upgradesSD_A14 V4SD_A13 V3SD_A12 Y2 Address inputsSD_A11 V1SD_A10 T3SD_A9 W2SD_A8 W1SD_A7 Y1SD_A6 U1SD_A5 U4SD_A4 U2SD_A3 U3SD_A2 R1SD_A1 T4SD_A0 R2
