74 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User GuideUG334 (v1.1) June 19, 2008Chapter 9: Analog Capture Circuit RSPI Control InterfaceFigure 9-3 highlights the SPI-based communications interface with the amplifier. The gainfor each amplifier is sent as an eight-bit command word, consisting of two four-bit fields.The most-significant bit, B3, is sent first.The AMP_DOUT output from the amplifier echoes the previous gain settings. Thesevalues can be ignored for most applications.The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see Figure 9-4). Theamplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal.The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.-5 0 0 1 1 1.4 1.9-10 0 1 0 0 1.525 1.775-20 0 1 0 1 1.5875 1.7125-50 0 1 1 0 1.625 1.675-100 0 1 1 1 1.6375 1.6625Table 9-2: Programmable Gain Settings for Pre-Amplifier (Continued)Gain A3 A2 A1 A0 Input Voltage RangeB3 B2 B1 B0 Minimum MaximumFigure 9-3: SPI Serial Interface to Amplifier7FPGAMaster0A1 A2 A3A0 B1 B2 B3B0A Gain B GainSlave: LTC2624-1AMP_DOUTSPI_MOSIAMP_CSSPI_SCKUG334_c9_03_052407Figure 9-4: SPI Timing When Communicating with AmplifierSPI_SCKAMP_CSSPI_MOSIAMP_DOUT7 6 5 4 3 230 5050306 5 4 3 285 maxAll timing is minimum in nanoseconds unless otherwise noted.(from AMP)(from FPGA)Previous 7UG230_c10_04_022306
