Xilinx spartan-3a User Manual

Also see for Spartan-3A DSP FPGA Series: Datasheet User guide Getting started Technical reference guide User guide

Contents

112 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User GuideUG334 (v1.1) June 19, 2008Chapter 13: DDR2 SDRAM RReserve FPGA VREF PinsFive pins in I/O Bank 3 are dedicated as voltage reference inputs, VREF. These pins cannotbe used for general-purpose I/Os in a design. Prohibit the software from using these pinswith the constraints provided in Figure 13-5.5iSpecial Layout RecommendationsThe Xilinx Memory Interface Generator (MIG) tool, version 1.7 and later, generates DDR2SDRAM interfaces for Spartan-3A and Spartan-3AN FPGAs. The MIG implementationleverages the FPGA’s local clocking resources to capture the DDR2 SDRAM read data.Consequently, there is a close relationship between the memory data pins (SD_DQ<15:8>,SD_DQ_<7:0>) and their associated strobe signals. The MIG software automaticallyassigns pins based on this requirement and the Spartan-3A/3AN Starter Kit board isdesigned accordingly.The MIG core for Spartan-3A/3AN FPGAs includes a loopback signal to calibrate the readstrobe timing. The loopback signal uses two FPGA pins, labeled SD_LOOP_IN andSD_LOOP_OUT. For best performance, the length of the loop back trace must be equal tothe clock delay from the FPGA to the memory, plus the strobe delay from the memory backto the FPGA. Put another way, the loopback trace must be one round trip time to and fromthe memory. Also, the loopback signal should be in the center of the data interface pins forbest results, not near the edge or in another FPGA I/O bank. The Spartan-3A/3AN StarterKit board was designed accordingly.The Xilinx Memory Interface Generator (MIG) User Guide provides additional layoutrecommendations in Appendix A: “Memory Implementation Guidelines”.The board layout has been optimized for reaching frequencies above 133 MHz and167 MHz. It can actually achieve the DDR400 performance level of 200 MHz or 400 Mbpsper I/O, with an optimized memory interface controller. It is recommended to get thelatest updates of the MIG tool that integrates the latest performance enhancements.• Memory Interface Generator (MIG)www.xilinx.com/support/download/index.htm(now included with the CORE Generator™ system)• UG086: Xilinx Memory Interface Generator (MIG) User Guide(included with MIG)• XAPP458: Implementing DDR2-400 Memory Interfaces in Spartan-3A FPGAswww.xilinx.com/support/documentation/application_notes/xapp458.pdfFigure 13-5: UCF Location Constraints for FPGA VREF Pins# Prohibit VREF pins on FPGA I/O Bank 3CONFIG PROHIBIT = H7;CONFIG PROHIBIT = J1;CONFIG PROHIBIT = J8;CONFIG PROHIBIT = L8;CONFIG PROHIBIT = N1;CONFIG PROHIBIT = R6;CONFIG PROHIBIT = T1;CONFIG PROHIBIT = T6;