Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com 75UG334 (v1.1) June 19, 2008Analog-to-Digital Converter (ADC)RUCF Location ConstraintsFigure 9-5 provides the User Constraint File (UCF) constraints for the amplifier interface,including the I/O pin assignment and I/O standard used.Analog-to-Digital Converter (ADC)The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneouslywhen the AD_CONV signal is applied.InterfaceTable 9-3 lists the interface signals between the FPGA and the ADC. The SPI_SCK signal isshared with other devices on the SPI bus. The active-High AD_CONV signal is the active-Low slave select input to the DAC. The DAC_CLR signal is the active-Low, asynchronousreset input to the DAC.SPI Control InterfaceFigure 9-6 provides an example SPI bus transaction to the ADC.When the AD_CONV signal goes High, the ADC simultaneously samples both analogchannels. The results of this conversion are not presented until the next time AD_CONV isasserted, a latency of one sample. The maximum sample rate is approximately 1.5 MHz.The ADC presents the digital representation of the sampled analog values as a 14-bit, two’scomplement binary value.Figure 9-5: UCF Location Constraints for the Pre-amplifier Interface (AMP)NET "SPI_MOSI" LOC = "AB14"| IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;NET "AMP_CS" LOC = "W6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;NET "SPI_SCK" LOC = "AA20"| IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;NET "AMP_SHDN" LOC = "W15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;NET "AMP_DOUT" LOC = "T7" | IOSTANDARD = LVCMOS33 ;Table 9-3: ADC Interface SignalsSignal FPGA Pin Direction DescriptionSPI_SCK AA20 FPGAÆADC ClockAD_CONV Y6 FPGAÆADC Active-High, initiates conversion process.ADC_OUT D16 FPGAÅADC Serial data. Presents the digital representation of thesample analog values as two 14-bit two’scomplement binary values.
