44 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User GuideUG334 (v1.1) June 19, 2008Chapter 5: Character LCD Screen RCharacter LCD Interface SignalsTable 5-1 shows the interface character LCD interface signals.Voltage CompatibilityThe character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However,the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. TheLCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided bythe FPGA meet the 5V TTL voltage level requirements.The 390Ω series resistors on the data lines prevent overstressing on the FPGA andStrataFlash I/O pins when the character LCD drives a High logic value. The character LCDdrives the data lines when LCD_RW is High. Most applications treat the LCD as a write-only peripheral and never read from the display.UCF Location ConstraintsFigure 5-2 provides the UCF constraints for the Character LCD, including the I/O pinassignment and the I/O standard used.Table 5-1: Character LCD InterfaceSignal Name FPGA Pin FunctionLCD_DB<7> Y15 Data bit DB7LCD_DB<6> AB16 Data bit DB6LCD_DB<5> Y16 Data bit DB5LCD_DB<4> AA12 Data bit DB4LCD_DB<3> AB12 Data bit DB3 When using the four-bitinterface, drive these signalsHigh.LCD_DB<2> AB17 Data bit DB2LCD_DB<1> AB18 Data bit DB1LCD_DB<0> Y13 Data bit DB0LCD_E AB4 Read/Write Enable Pulse0: Disabled1: Read/Write operation enabledLCD_RS Y14 Register Select0: Instruction register during write operations.Busy Flash during read operations1: Data for read or write operationsLCD_RW W13 Read/Write Control0: Write, LCD accepts data1: Read, LCD presents data
