Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com 89UG334 (v1.1) June 19, 2008Creating and Programming Configuration Images for Parallel FlashRCreating and Programming Configuration Images for ParallelFlashDue to the high fanout of the CCLK signal on the Starter Kit board, it is recommended thatthe FPGA CCLK frequency be set to 1 MHz when creating FPGA configuration images forthe parallel Flash. See UG332 for information on typical configuration clock speedssupported for custom boards.Refer to the “Master BPI Mode” chapter in the Spartan-3 Generation Configuration User Guidefor information on how to create and format FPGA configuration images for parallel Flash.To program the parallel Flash memory, see the associated design example.• UG332: Spartan-3 Generation Configuration User Guidewww.xilinx.com/support/documentation/user_guides/ug332.pdf• Design Example: Programmer for the STMicroelectronics M29DW323DT ParallelNOR Flashwww.xilinx.com/products/boards/s3astarter/reference_designs.htm#parallel_flash_programmerRelated ResourcesRefer to the following links for additional information:• STMicroelectronics M29DW323DT 32 Mbit Parallel NOR Flash PROMwww.numonyx.com/Documents/Datasheets/M29DW323D.pdf• Design Example: Programmer for the STMicroelectronics M29DW323DT ParallelNOR Flashwww.xilinx.com/products/boards/s3astarter/reference_designs.htm#parallel_flash_programmer
