64 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User GuideUG334 (v1.1) June 19, 2008Chapter 7: RS-232 Serial Ports RFigure 7-1 shows the connection between the FPGA and the two DB9 connectors. TheFPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device,which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise,the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. Aseries resistor between the Maxim output pin and the FPGA’s RXD pin protects againstinadvertent logic conflicts such as accidentally connecting the board using a null-modemcable. In this example, both the FPGA and the external serial device are driving data on thetransmit line.Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSRsignals connect together, as shown in Figure 7-1. Similarly, the port’s RTS and CTS signalsconnect together.UCF Location ConstraintsFigure 7-2 and Figure 7-3 provide the UCF constraints for the DTE and DCE RS-232 ports,respectively, including the I/O pin assignment and the I/O standard used.Figure 7-2: UCF Location Constraints for DTE RS-232 Serial PortFigure 7-3: UCF Location Constraints for DCE RS-232 Serial PortNET "RS232_DTE_RXD" LOC = "F16" | IOSTANDARD = LVCMOS33 ;NET "RS232_DTE_TXD" LOC = "E15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;NET "RS232_DCE_RXD" LOC = "E16" | IOSTANDARD = LVCMOS33 ;NET "RS232_DCE_TXD" LOC = "F15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW;
