Xilinx spartan-3a User Manual

Also see for Spartan-3A DSP FPGA Series: Datasheet User guide Getting started Technical reference guide User guide

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32 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User GuideUG334 (v1.1) June 19, 2008Chapter 2: Switches, Buttons, and Rotary Knob RAWAKE LEDThe yellow-colored AWAKE LED connects to the FPGA’s AWAKE pin and is used if theFPGA Suspend mode is enabled in the bitstream. If the Suspend mode is not used, then theFPGA’s AWAKE pin is available as a full user-I/O pin.If the FPGA is not yet configured, the FPGA’s AWAKE pin is dimly lit because pull-upresistors are enabled during configuration. The FPGA’s PUDC_B pin is connected to GNDon the board.To light the AWAKE LED in an application, drive the AWAKE pin High.INIT_B LEDThe red-colored INIT_B LED serves multiple purposes:• At power-up or when the PROG_B button is pressed, the LED flashes momentarilywhile the FPGA clears its configuration memory.• If configuration fails for any reason, then the FPGA’s DONE LED will be unlit and theINIT_B LED will light. This indicates that the FPGA could not successfully configure.• After the FPGA successfully completes, the INIT_B pin is available as a general-purpose user-I/O pin. If no signal drives INIT_B, then it is defined as an input pinwith a pull-down resistor. It might appear that the LED dimly glows. Drive theINIT_B pin High to turn off the LED or Low to light the LED.• If using the Readback CRC feature, the INIT_B pin is reserved and signals a CRC errorafter configuration. If such an error occurs, the FPGA drives INIT_B Low, lighting theLED.If using the INIT_B pin as a user-I/O pin after configuration, drive the pin Low to light theLED and High to shut it off. Jumper J46, shown in Table 4-2, page 40, must be in either the“Disabled” or “Enabled during Configuration” setting.The “Always Enabled” setting for Jumper J46 allows the FPGA to read additional datafrom the Platform Flash PROM after configuration, as described in Xilinx application noteXAPP694.Caution! The FPGA’s INIT_B pin also connects to the Platform Flash PROM’s OE/RESET pin.If the jumper controlling the Platform Flash PROM, jumper J46 in Table 4-2, page 40, is set to“Always Enabled,” then the INIT_B signal controls the PROM’s active-Low output-enable (OE)input or active-High RESET input.• XAPP694: Reading User Data from Configuration PROMswww.xilinx.com/support/documentation/application_notes/xapp694.pdfUCF Location ConstraintsFigure 2-15 provides the UCF constraints for the optional LEDs, including the I/O pinassignment, the I/O standard used, the output slew rate, and the output drive current. TheENABLE_SUSPEND constraint must be set to NO in order to use FPGA_AWAKE LED.Figure 2-15: UCF Constraints for Optional Discrete LEDsNET "FPGA_INIT_B" LOC = "V13" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;# The AWAKE LED is only available if Suspend mode is disabledCONFIG ENABLE_SUSPEND = NO ;NET "FPGA_AWAKE" LOC = "AB15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;