Xilinx spartan-3a User Manual Manual pdf 6 page image
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Xilinx spartan-3a User Manual

Also see for Spartan-3A DSP FPGA Series: DatasheetUser guideGetting startedTechnical reference guideUser guide

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Acknowledgments
  7. Additional Resources
  8. Getting Started
  9. Operating the Default Demonstration Design
  10. Select MultiBoot Configuration Image
  11. Scroll or Rotate Graphic
  12. LCD Screen Control Option
  13. RS-232 Serial Port Control Option
  14. Design Trade-Offs
  15. Choose a Spartan-3 Generation Starter Kit Board for your Needs
  16. Other Spartan-3 Generation Development Boards
  17. Related Resources
  18. Slide Switches
  19. SUSPEND Switch
  20. Push-Button Switches
  21. PROG_B Push-Button Switch
  22. Rotary Shaft Encoder
  23. UCF Location Constraints
  24. Operation
  25. AWAKE LED
  26. Overview
  27. Clock Connections
  28. Clock Period Constraints
  29. Configuration Mode Jumpers
  30. Xilinx Platform Flash Configuration PROM(s)
  31. DONE Pin LED
  32. Platform Flash Programming Example
  34. Character LCD Interface Signals
  35. LCD Controller
  36. Command Set
  37. Disabled
  38. Display On/Off
  39. Function Set
  41. Transferring Eight-Bit Data over the Four-Bit Interface
  42. Power-On Initialization
  43. Disabling the Unused LCD
  44. Signal Timing for a 60 Hz, 640x480 VGA Display
  45. VGA Signal Timing
  49. Keyboard
  50. Mouse
  51. Voltage Supply
  53. Digital Outputs from Analog Inputs
  54. Programmable Pre-Amplifier
  55. SPI Control Interface
  58. Connecting Analog Inputs
  59. SPI Communication
  60. Interface Signals
  61. Communication Protocol
  62. Specifying the DAC Output Voltage
  63. Flash Connections
  64. Shared SPI Flash and Platform Flash Data Line
  66. Data
  67. Creating and Programming Configuration Images for Parallel Flash
  68. Chapter 12: SPI Serial Flash
  69. SPI Flash PROM Select Jumpers (J1)
  72. Direct Programming Method
  73. Using a Separate JTAG Parallel Programming Cable (Optional)
  74. Direct SPI Flash Programming Using iMPACT
  75. Indirect Programming Method
  76. Indirect SPI Flash Programming Using iMPACT
  78. DDR2 SDRAM Connections
  81. Special Layout Recommendations
  83. Ethernet PHY Connections
  84. MicroBlaze Ethernet IP Cores
  86. Hirose 100-Pin FX2 Edge Connector (J17)
  87. Connector Pinout and FPGA Connections
  88. FX2-Connector Compatible Boards
  90. Differential I/O Connectors
  91. Using Differential Inputs
  92. Using Differential Outputs
  93. Conductor Cable Assemblies (2x17)
  94. Six-Pin Accessory Headers
  95. J20 Header
  97. Supported Audio Devices
  98. FPGA Connections
  99. Chapter 17: Voltage Supplies
  100. Measuring Power Across Voltage Supply Jumpers
  101. Possible Applications
  102. Restoring Default Voltages
Xilinx spartan-3a User Manual Manual pdf 6 page image
6 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User GuideUG334 (v1.1) June 19, 2008RRelated Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Chapter 10: Digital-to-Analog Converter (DAC)SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80SPI Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Specifying the DAC Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Chapter 11: Parallel NOR Flash PROMFlash Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Shared SPI Flash and Platform Flash Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Creating and Programming Configuration Images for Parallel Flash . . . . . . . . . 89Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Chapter 12: SPI Serial FlashSPI Flash PROM Select Jumpers (J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Shared SPI Flash and Platform Flash Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Jumper Settings to Configure FPGA from Selected SPI Flash PROM . . . . . . . . . . . . . 94UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Creating and Programming Configuration Images for SPI Serial Flash . . . . . . . 95SPI Flash PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Direct Programming Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Using Embedded USB JTAG Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Using a Separate JTAG Parallel Programming Cable (Optional) . . . . . . . . . . . . . . . . . . 97Direct SPI Flash Programming Using iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Indirect Programming Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Jumper Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Indirect SPI Flash Programming Using iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Chapter 13: DDR2 SDRAMDDR2 SDRAM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Reserve FPGA VREF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Special Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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