126 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User GuideUG334 (v1.1) June 19, 2008Chapter 15: Expansion Connectors Rbehaves like an internal termination resistor of approximately 100Ω . On-chip differentialtermination is only available on full I/O pairs, not on Input-only pairs.Differential inputs are powered by the VCCAUX supply, which is 3.3V by default.Differential inputs are available in any I/O bank.Using Differential OutputsDifferential inputs are supported within any I/O bank. However, with Spartan-3A andSpartan-3AN FPGAs, differential outputs are only supported on I/O Bank 0 or 2.Differential outputs are powered by the respective I/O bank output voltage, VCCO. On theSpartan-3A/3AN Starter Kit board, I/O Banks 0, 1, and 2 are all powered by a 3.3V supply.IDifferential Trace Layout ConsiderationsFigure 15-6 shows board layout extracted from the Starter Kit board that highlights thedifferential I/O signal traces. These traces were routed for optimal signal integrity.• All differential pairs are routed with matched 100Ω impedance on the top board layerfor maximum performance.• The traces were routed to avoid via where possible.• The trace lengths for differential pairs routed to a specific header (either the “Receive”or “Transmit” header) were matched to within 0.25 inches.• The differential signals connections on the FPGA use the outer two ball rings to avoidbreakout congestion.• The “Receive” differential clock pair, highlighted in blue in Figure 15-6, connects to adifferential global clock input pair, GCLK7 and GCLK8. Using these global clockFigure 15-4: Differential Input Termination OptionsLxxP_0LxxN_0 SignalLxxP_0LxxN_0 SignalPads for 100Ωsurface-mount resistorDifferential termination(~100Ω)a) External 100Ω termination resistor b) On-chip differential input terminationFPGA FPGAUG334_c15_04_052407PAD PADIBUFDS orBUFGDS(not provided on the Starter Kit)IBUFDS orBUFGDSFigure 15-5: Differential OutputsLxxP_2LxxN_2PADSignalFPGAUG330_c12_06_072706OBUFDS
