227CHAPTER 9 8-BIT TIMER/EVENT COUNTERSTable 9-7. 8-Bit Timer/Event Counter 2 Interval TimeMinimum Interval Time Maximum Interval Time ResolutionMCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 00 0 0 0 TI2 input cycle 2 8 × TI2 input cycle TI2 input edge cycle0 0 0 1 TI2 input cycle 2 8 × TI2 input cycle TI2 input edge cycle2 × 1/f X 2 2 × 1/f X 2 9 × 1/f X 2 10 × 1/f X 2 × 1/f X 2 2 × 1/f X(400 ns) (800 ns) (102.4μs) (204.8μs) (400 ns) (800 ns)2 2 × 1/f X 2 3 × 1/f X 2 10 × 1/f X 2 11 × 1/f X 2 2 × 1/f X 2 3 × 1/f X(800 ns) (1.6μs) (204.8μs) (409.6μs) (800 ns) (1.6μs)2 3 × 1/f X 2 4 × 1/f X 2 11 × 1/f X 2 12 × 1/f X 2 3 × 1/f X 2 4 × 1/f X(1.6μs) (3.2μs) (409.6μs) (819.2μs) (1.6μs) (3.2μs)2 4 × 1/f X 2 5 × 1/f X 2 12 × 1/f X 2 13 × 1/f X 2 4 × 1/f X 2 5 × 1/f X(3.2μs) (6.4μs) (819.2μs) (1.64 ms) (3.2μs) (6.4μs)2 5 × 1/f X 2 6 × 1/f X 2 13 × 1/f X 2 14 × 1/f X 2 5 × 1/f X 2 6 × 1/f X(6.4μs) (12.8μs) (1.64 ms) (3.28 ms) (6.4μs) (12.8μs)2 6 × 1/f X 2 7 × 1/f X 2 14 × 1/f X 2 15 × 1/f X 2 6 × 1/f X 2 7 × 1/f X(12.8μs) (25.6μs) (3.28 ms) (6.55 ms) (12.8μs) (25.6μs)2 7 × 1/f X 2 8 × 1/f X 2 15 × 1/f X 2 16 × 1/f X 2 7 × 1/f X 2 8 × 1/f X(25.6μs) (51.2μs) (6.55 ms) (13.1 ms) (25.6μs) (51.2μs)2 8 × 1/f X 2 9 × 1/f X 2 16 × 1/f X 2 17 × 1/f X 2 8 × 1/f X 2 9 × 1/f X(51.2μs) (102.4μs) (13.1 ms) (26.2 ms) (51.2μs) (102.4μs)2 9 × 1/f X 2 10 × 1/f X 2 17 × 1/f X 2 18 × 1/f X 2 9 × 1/f X 2 10 × 1/f X(102.4μs) (204.8μs) (26.2 ms) (52.4 ms) (102.4μs) (204.8μs)2 11 × 1/f X 2 12 × 1/f X 2 19 × 1/f X 2 20 × 1/f X 2 11 × 1/f X 2 12 × 1/f X(409.6μs) (819.2μs) (104.9 ms) (209.7 ms) (409.6μs) (819.2μs)Other than above Setting prohibitedRemarks 1. f X : Main system clock oscillation frequency2. MCS : Bit 0 of oscillation mode selection register (OSMS)3. TCL14 to TCL17 : Bits 4 to 7 of timer clock selection register 1 (TCL1)4. Values in parentheses when operated at f X = 5.0 MHz0 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1TCL17 TCL16 TCL15 TCL14
