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NEC PD78056F User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. CHAPTER 1 OUTLINE ( PD78058F SUBSERIES)
  21. Applications
  22. Quality Grade
  23. Pin Configuration (Top View)
  24. K/0 Series Expansion
  25. Block Diagram
  26. Outline of Function
  27. Differences Between the PD78058F and PD78058F(A)
  28. Mask Options
  29. CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES)
  30. Ordering Information
  36. Differences Between the PD78058FY and PD78058FY(A)
  37. Mask Options of Mask ROM Versions
  38. CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES)
  39. PROM programming mode pins (PROM versions only)
  40. Description of Pin Functions
  41. P10 to P17 (Port 1)
  42. P30 to P37 (Port 3)
  43. P40 to P47 (Port 4)
  44. P70 to P72 (Port 7)
  45. P120 to P127 (Port 12)
  46. AV DD
  47. IC (Mask ROM version only)
  48. Input/output Circuits and Recommended Connection of Unused Pins
  49. List of Pin Input/Output Circuit
  50. CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES)
  52. P00 to P07 (Port 0)
  53. P20 to P27 (Port 2)
  55. P50 to P57 (Port 5)
  57. P130 and P131 (Port 13)
  58. AV SS
  60. Pin Input/Output Circuit Types
  62. CHAPTER 5 CPU ARCHITECTURE
  63. Memory Map ( PD78058F, 78058FY)
  64. Memory Map ( PD78P058F, PD78P058FY)
  65. Internal program memory space
  66. Internal data memory space
  67. Data memory addressing
  68. Data Memory Addressing ( PD78058F, 78058FY)
  69. Data Memory Addressing ( PD78P058F, 78P058FY)
  70. Processor Registers
  71. Stack Pointer Format
  72. General registers
  73. General Register Configuration
  74. Special Function Register (SFR)
  75. Special-Function Register List
  76. Instruction Address Addressing
  77. Immediate addressing
  78. Table indirect addressing
  79. Register addressing
  80. Operand Address Addressing
  82. Direct addressing
  83. Short direct addressing
  84. Special-Function Register (SFR) addressing
  85. Register indirect addressing
  86. Based addressing
  87. Based indexed addressing
  88. CHAPTER 6 PORT FUNCTIONS
  89. Port Functions ( PD78058F Subseries)
  90. Port Functions ( PD78058FY Subseries)
  91. Port Configuration
  92. P00 and P07 Block Diagram
  93. Port 1
  94. Port 2 ( PD78058F Subseries)
  95. P22 and P27 Block Diagram
  96. Port 2 ( PD78058FY Subseries)
  98. Port 3
  99. Port 4
  100. Port 5
  101. Port 6
  102. P60 to P63 Block Diagram
  103. Port 7
  104. P71 and P72 Block Diagram
  105. Port 12
  106. Port 13
  107. Port Function Control Registers
  108. Port Mode Register and Output Latch Settings When Using Alternate Functions
  109. Port Mode Register Format
  110. Pull-Up Resistor Option Register Format
  111. Memory Expansion Mode Register Format
  112. Key Return Mode Register Format
  113. Port Function Operations
  114. Operations on input/output port
  115. CHAPTER 7 CLOCK GENERATOR
  116. Block Diagram of Clock Generator
  117. Clock Generator Control Register
  118. Processor Clock Control Register Format
  119. Oscillation Mode Selection Register Format
  120. Main System Clock Waveform due to Writing to OSMS
  121. System Clock Oscillator
  122. Subsystem clock oscillator
  123. Scaler
  124. Clock Generator Operations
  125. Main system clock operations
  126. Subsystem clock operations
  127. Maximum Time Required for CPU Clock Switchover
  128. System clock and CPU clock switching procedure
  129. CHAPTER 8 16-BIT TIMER/EVENT COUNTER
  130. Timer/Event Counter Operation
  131. Bit Timer/Event Counter Functions
  132. Bit Timer/Event Counter Configuration
  133. Bit Timer/Event Counter Block Diagram
  134. Bit Timer/Event Counter Output Control Circuit Block Diagram
  135. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
  136. Bit Timer/Event Counter Control Registers
  137. Timer Clock Selection Register 0 Format
  138. Bit Timer Mode Control Register Format
  139. Capture/Compare Control Register 0 Format
  140. Bit Timer Output Control Register Format
  141. Port Mode Register 3 Format
  142. External Interrupt Mode Register 0 Format
  143. Sampling Clock Select Register Format
  144. Bit Timer/Event Counter Operations
  145. Interval Timer Configuration Diagram
  146. PWM output operations
  147. Control Register Settings for PWM Output Operation
  148. Example of D/A Converter Configuration with PWM Output
  149. PPG output operation
  150. Pulse width measurement operations
  151. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
  152. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
  153. Control Register Settings for Pulse Width Measurement by Means of Restart
  154. External event counter operation
  155. External Event Counter Configuration Diagram
  156. Square-wave output operation
  157. Square-Wave Output Operation Timing
  158. One-shot pulse output operation
  159. Timing of One-Shot Pulse Output Operation Using Software Trigger
  160. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
  161. Bit Timer/Event Counter Operating Precautions
  162. Capture Register Data Retention Timing
  163. Operation Timing of OVF0 Flag
  164. CHAPTER 9 8-BIT TIMER/EVENT COUNTERS
  165. Bit Timer/Event Counter Interval Times
  166. Bit Timer/Event Counter Square-Wave Output Ranges
  167. bit timer/event counter mode
  170. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
  172. Timer Clock Select Register 1 Format
  176. Bit Timer/Event Counter Operation
  177. Bit Timer/Event Counter 1 Interval Time
  178. Bit Timer/Event Counter 2 Interval Time
  179. External Event Counter Operation Timings (with Rising Edge Specified)
  182. Interval Timer Operation Timing
  184. TM1 and TM2) are Used as 16-Bit Timer/Event Counter
  186. Cautions on 8-Bit Timer/Event Counters
  187. Timing After Compare Register Change During Timer Count Operation
  188. CHAPTER 10 WATCH TIMER
  189. Watch Timer Configuration
  190. Watch Timer Block Diagram
  191. Timer Clock Select Register 2 Format
  192. Watch Timer Mode Control Register Format
  193. Watch Timer Operations
  194. CHAPTER 11 WATCHDOG TIMER
  195. Interval Times
  196. Watchdog Timer Configuration
  197. Watchdog Timer Control Registers
  199. Watchdog Timer Mode Register Format
  200. Watchdog Timer Operations
  201. Interval timer operation
  202. CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
  203. Clock Output Control Circuit Configuration
  204. Timer Clock Select Register 0 Format
  206. CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
  207. Buzzer Output Function Control Registers
  210. CHAPTER 14 A/D CONVERTER
  211. A/D Converter Configuration
  212. A/D Converter Block Diagram
  213. A/D Converter Control Registers
  214. A/D Converter Mode Register Format
  215. A/D Converter Input Select Register Format
  216. External Interrupt Mode Register 1 Format
  217. A/D Converter Operations
  218. A/D Converter Basic Operation
  219. Input voltage and conversion results
  220. A/D converter operating mode
  221. A/D Conversion by Software Start
  222. A/D Converter Cautions
  223. Connection of Analog Input Pin
  224. A/D Conversion End Interrupt Request Generation Timing
  225. CHAPTER 15 D/A CONVERTER
  226. D/A Converter Configuration
  227. D/A Converter Control Registers
  228. Operations of D/A Converter
  229. Cautions Related to D/A Converter
  230. CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES)
  231. Serial Interface Channel 0 Functions
  232. Serial Bus Interface (SBI) System Configuration Example
  233. Serial Interface Channel 0 Configuration
  234. Serial Interface Channel 0 Block Diagram
  235. Serial Interface Channel 0 Control Registers
  236. Timer Clock Select Register 3 Format
  237. Serial Operating Mode Register 0 Format
  238. Serial Bus Interface Control Register Format
  239. Interrupt Timing Specify Register Format
  240. Serial Interface Channel 0 Operations
  241. wire serial I/O mode operation
  242. Wire Serial I/O Mode Timings
  243. Circuit of Switching in Transfer Bit Order
  244. SBI mode operation
  245. SBI Transfer Timings
  246. Bus Release Signal
  247. Addresses
  248. Commands
  249. Acknowledge Signal
  250. BUSY and READY Signals
  251. RELT, CMDT, RELD, and CMDD Operations (Master)
  252. ACKT Operation
  253. ACKE Operations
  254. ACKD Operations
  255. Various Signals in SBI Mode
  256. Pin Configuration
  257. Address Transmission from Master Device to Slave Device (WUP = 1)
  258. Command Transmission from Master Device to Slave Device
  259. Data Transmission from Master Device to Slave Device
  260. Data Transmission from Slave Device to Master Device
  261. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
  263. RELT and CMDT Operations
  264. SCK0/P27 pin output manipulation
  265. CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES)
  269. Serial Interface Channel 0 Interrupt Request Signal Generation
  275. Operation stop mode
  282. Start Condition
  283. Stop Condition
  284. Wait Signal
  286. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)
  287. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)
  288. Start Condition Output
  289. Slave Wait Release (Transmission)
  290. Slave Wait Release (Reception)
  291. SCK0/SCL/P27 pin output manipulation
  292. Logic Circuit of SCL Signal
  293. CHAPTER 18 SERIAL INTERFACE CHANNEL 1
  294. Serial Interface Channel 1 Configuration
  295. Serial Interface Channel 1 Block Diagram
  296. Serial Interface Channel 1 Control Registers
  298. Serial Operating Mode Register 1 Format
  299. Automatic Data Transmit/Receive Control Register Format
  300. Automatic Data Transmit/Receive Interval Specify Register Format
  301. Serial Interface Channel 1 Operations
  305. wire serial I/O mode operation with automatic transmit/receive function
  306. Basic Transmission/Reception Mode Operation Timings
  307. Basic Transmission/Reception Mode Flowchart
  308. Basic Transmission Mode Operation Timings
  309. Basic Transmission Mode Flowchart
  310. Repeat Transmission Mode Operation Timing
  311. Repeat Transmission Mode Flowchart
  312. Automatic Transmission/Reception Suspension and Restart
  313. System Configuration When the Busy Control Option Is Used
  314. Operation Timings When Using Busy Control Option (BUSY0 = 0)
  315. Busy Signal and Wait Cancel (When BUSY0 = 0)
  316. Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0)
  317. Automatic Transmit/Receive Interval Time
  318. Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
  319. Interval Timing Through CPU Processing (When the External Clock Is Operating)
  320. CHAPTER 19 SERIAL INTERFACE CHANNEL 2
  321. Serial Interface Channel 2 Configuration
  322. Serial Interface Channel 2 Block Diagram
  323. Baud Rate Generator Block Diagram
  324. Serial Interface Channel 2 Control Registers
  325. Asynchronous Serial Interface Mode Register Format
  326. Serial Interface Channel 2 Operating Mode Settings
  327. Asynchronous Serial Interface Status Register Format
  328. Baud Rate Generator Control Register Format
  329. Relationship Between Main System Clock and Baud Rate
  330. Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
  331. Serial Interface Channel 2 Operation
  332. Asynchronous serial interface (UART) mode
  335. Asynchronous Serial Interface Transmit/Receive Data Format
  336. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
  337. Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
  338. Receive Error Timing
  339. Receive Buffer Register (RXB) Status and Receive Completion Interrupt Request (INTSR Generation When Receiving Is Terminated
  340. wire serial I/O mode
  341. Wire Serial I/O Mode Timing
  343. Restrictions on using UART mode
  344. Period that Reading Receive Buffer Register Is Prohibited
  345. CHAPTER 20 REAL-TIME OUTPUT PORT
  346. Real-Time Output Port Configuration
  347. Real-time Output Buffer Register Configuration
  348. Real-Time Output Port Control Registers
  349. Real-time Output Port Control Register Format
  350. CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
  351. Interrupt Sources and Configuration
  352. Basic Configuration of Interrupt Function
  353. Interrupt Function Control Registers
  354. Interrupt Request Flag Register Format
  355. Interrupt Mask Flag Register Format
  356. Priority Specify Flag Register Format
  360. Noise Elimination Circuit Input/Output Timing (During Rising Edge Detection)
  361. Program Status Word Format
  362. Interrupt Servicing Operations
  363. Flowchart from the Time a Non-maskable Interrupt Request Is Generated Until It Is Received
  364. Non-Maskable Interrupt Request Acknowledge Operation
  365. Maskable Interrupt request reception
  366. Interrupt Request Acknowledge Processing Algorithm
  367. Interrupt Request Acknowledge Timing (Minimum Time)
  368. Software interrupt request acknowledge operation
  369. Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing
  370. Multiple Interrupt Example
  371. Interrupt request reserve
  372. Test Functions
  373. Format of Interrupt Request Flag Register 1L
  374. Test input signal acknowledge operation
  375. CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
  376. Memory Map When Using External Device Expansion Function
  377. External Device Expansion Function Control Register
  378. Memory Size Switching Register Format
  379. External Device Expansion Function Timing
  380. Instruction Fetch from External Memory
  381. External Memory Read Timing
  382. External Memory Write Timing
  383. External Memory Read Modify Write Timing
  384. CHAPTER 23 STANDBY FUNCTION
  385. Standby function control register
  386. Standby Function Operations
  387. HALT Mode Clear upon Interrupt Request Generation
  388. HALT Mode Release by RESET Input
  389. STOP mode
  390. STOP Mode Release by Interrupt Request Generation
  391. Release by STOP Mode RESET Input
  392. CHAPTER 24 RESET FUNCTION
  393. Timing of Reset Input by RESET Input
  394. Hardware Status After Reset
  395. CHAPTER 25 ROM CORRECTION
  396. Correction Address Registers 0 and 1 Format
  397. ROM Correction Control Registers
  398. ROM Correction Application
  399. Initialization Routine
  400. ROM Correction Operation
  401. ROM Correction Example
  402. Program Execution Flow
  403. Program Transition Diagram (When Two Places Are Corrected)
  404. Cautions on ROM Correction
  405. CHAPTER 26 PD78P058F, 78P058FY
  406. Memory Size Switching Register
  407. Internal Expansion RAM Size Switching Register
  408. PROM Programming
  409. PROM write procedure
  410. Page Program Mode Timing
  411. Byte Program Mode Flowchart
  412. Byte Program Mode Timing
  413. PROM read procedure
  414. Screening of One-Time PROM Versions
  415. CHAPTER 27 INSTRUCTION SET
  416. Legends Used in Operation List
  417. Description of "operation" column
  418. Operation List
  419. Instructions Listed by Addressing Type
  420. APPENDIX A DIFFERENCES AMONG PD78054, 78058F, AND 780058 SUBSERIES
  421. APPENDIX B DEVELOPMENT TOOLS
  422. B-1 Development Tool Configuration
  423. B.1 Language Processing Software
  424. B.2 PROM Programming Tool
  425. B.3 Debugging Tool
  426. B.3.2 Software
  427. B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
  428. B-2 EV-9200GC-80 Drawings (For Reference Only)
  429. B-3 EV-9200GC-80 Footprints (For Reference Only)
  430. B-4 TGK-080SDW Drawings (For Reference) (unit: mm)
  431. APPENDIX C EMBEDDED SOFTWARE
  432. C.1 Real-time OS
  433. APPENDIX D REGISTER INDEX
  434. APPENDIX E REVISION HISTORY
NEC PD78056F User Manual Manual pdf 532 page image
532CHAPTER 25 ROM CORRECTIONNoYesInternal ROM program startDoes fetch addressmatch with correctionaddress?Set correction status flagCorrection branch(branch to address F7FDH)Correction program executionROM correctionFigure 25-7. ROM Correction Operation
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This manual is suitable for:
PD78056FPD78056FYPD78058FPD78058F(A)PD78058FYPD78058FY(A)PD78P058FPD78P058FY
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