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NEC PD78056F User Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. Table Of Contents
  17. Table Of Contents
  18. Table Of Contents
  19. Table Of Contents
  20. CHAPTER 1 OUTLINE ( PD78058F SUBSERIES)
  21. Applications
  22. Quality Grade
  23. Pin Configuration (Top View)
  24. K/0 Series Expansion
  25. Block Diagram
  26. Outline of Function
  27. Differences Between the PD78058F and PD78058F(A)
  28. Mask Options
  29. CHAPTER 2 OUTLINE ( PD78058FY SUBSERIES)
  30. Ordering Information
  31. Differences Between the PD78058FY and PD78058FY(A)
  32. Mask Options of Mask ROM Versions
  33. CHAPTER 3 PIN FUNCTION ( PD78058F SUBSERIES)
  34. PROM programming mode pins (PROM versions only)
  35. Description of Pin Functions
  36. P10 to P17 (Port 1)
  37. P30 to P37 (Port 3)
  38. P40 to P47 (Port 4)
  39. P70 to P72 (Port 7)
  40. P120 to P127 (Port 12)
  41. AV DD
  42. IC (Mask ROM version only)
  43. Input/output Circuits and Recommended Connection of Unused Pins
  44. List of Pin Input/Output Circuit
  45. CHAPTER 4 PIN FUNCTION ( PD78058FY SUBSERIES)
  46. P00 to P07 (Port 0)
  47. P20 to P27 (Port 2)
  48. P50 to P57 (Port 5)
  49. P130 and P131 (Port 13)
  50. AV SS
  51. Pin Input/Output Circuit Types
  52. CHAPTER 5 CPU ARCHITECTURE
  53. Memory Map ( PD78058F, 78058FY)
  54. Memory Map ( PD78P058F, PD78P058FY)
  55. Internal program memory space
  56. Internal data memory space
  57. Data memory addressing
  58. Data Memory Addressing ( PD78058F, 78058FY)
  59. Data Memory Addressing ( PD78P058F, 78P058FY)
  60. Processor Registers
  61. Stack Pointer Format
  62. General registers
  63. General Register Configuration
  64. Special Function Register (SFR)
  65. Special-Function Register List
  66. Instruction Address Addressing
  67. Immediate addressing
  68. Table indirect addressing
  69. Register addressing
  70. Operand Address Addressing
  71. Direct addressing
  72. Short direct addressing
  73. Special-Function Register (SFR) addressing
  74. Register indirect addressing
  75. Based addressing
  76. Based indexed addressing
  77. CHAPTER 6 PORT FUNCTIONS
  78. Port Functions ( PD78058F Subseries)
  79. Port Functions ( PD78058FY Subseries)
  80. Port Configuration
  81. P00 and P07 Block Diagram
  82. Port 1
  83. Port 2 ( PD78058F Subseries)
  84. P22 and P27 Block Diagram
  85. Port 2 ( PD78058FY Subseries)
  86. Port 3
  87. Port 4
  88. Port 5
  89. Port 6
  90. P60 to P63 Block Diagram
  91. Port 7
  92. P71 and P72 Block Diagram
  93. Port 12
  94. Port 13
  95. Port Function Control Registers
  96. Port Mode Register and Output Latch Settings When Using Alternate Functions
  97. Port Mode Register Format
  98. Pull-Up Resistor Option Register Format
  99. Memory Expansion Mode Register Format
  100. Key Return Mode Register Format
  101. Port Function Operations
  102. Operations on input/output port
  103. CHAPTER 7 CLOCK GENERATOR
  104. Block Diagram of Clock Generator
  105. Clock Generator Control Register
  106. Processor Clock Control Register Format
  107. Oscillation Mode Selection Register Format
  108. Main System Clock Waveform due to Writing to OSMS
  109. System Clock Oscillator
  110. Subsystem clock oscillator
  111. Scaler
  112. Clock Generator Operations
  113. Main system clock operations
  114. Subsystem clock operations
  115. Maximum Time Required for CPU Clock Switchover
  116. System clock and CPU clock switching procedure
  117. CHAPTER 8 16-BIT TIMER/EVENT COUNTER
  118. Timer/Event Counter Operation
  119. Bit Timer/Event Counter Functions
  120. Bit Timer/Event Counter Configuration
  121. Bit Timer/Event Counter Block Diagram
  122. Bit Timer/Event Counter Output Control Circuit Block Diagram
  123. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
  124. Bit Timer/Event Counter Control Registers
  125. Timer Clock Selection Register 0 Format
  126. Bit Timer Mode Control Register Format
  127. Capture/Compare Control Register 0 Format
  128. Bit Timer Output Control Register Format
  129. Port Mode Register 3 Format
  130. External Interrupt Mode Register 0 Format
  131. Sampling Clock Select Register Format
  132. Bit Timer/Event Counter Operations
  133. Interval Timer Configuration Diagram
  134. PWM output operations
  135. Control Register Settings for PWM Output Operation
  136. Example of D/A Converter Configuration with PWM Output
  137. PPG output operation
  138. Pulse width measurement operations
  139. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
  140. Control Register Settings for Two Pulse Width Measurements with Free-Running Counter
  141. Control Register Settings for Pulse Width Measurement by Means of Restart
  142. External event counter operation
  143. External Event Counter Configuration Diagram
  144. Square-wave output operation
  145. Square-Wave Output Operation Timing
  146. One-shot pulse output operation
  147. Timing of One-Shot Pulse Output Operation Using Software Trigger
  148. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
  149. Bit Timer/Event Counter Operating Precautions
  150. Capture Register Data Retention Timing
  151. Operation Timing of OVF0 Flag
  152. CHAPTER 9 8-BIT TIMER/EVENT COUNTERS
  153. Bit Timer/Event Counter Interval Times
  154. Bit Timer/Event Counter Square-Wave Output Ranges
  155. bit timer/event counter mode
  156. Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1
  157. Timer Clock Select Register 1 Format
  158. Bit Timer/Event Counter Operation
  159. Bit Timer/Event Counter 1 Interval Time
  160. Bit Timer/Event Counter 2 Interval Time
  161. External Event Counter Operation Timings (with Rising Edge Specified)
  162. Interval Timer Operation Timing
  163. TM1 and TM2) are Used as 16-Bit Timer/Event Counter
  164. Cautions on 8-Bit Timer/Event Counters
  165. Timing After Compare Register Change During Timer Count Operation
  166. CHAPTER 10 WATCH TIMER
  167. Watch Timer Configuration
  168. Watch Timer Block Diagram
  169. Timer Clock Select Register 2 Format
  170. Watch Timer Mode Control Register Format
  171. Watch Timer Operations
  172. CHAPTER 11 WATCHDOG TIMER
  173. Interval Times
  174. Watchdog Timer Configuration
  175. Watchdog Timer Control Registers
  176. Watchdog Timer Mode Register Format
  177. Watchdog Timer Operations
  178. Interval timer operation
  179. CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT
  180. Clock Output Control Circuit Configuration
  181. Timer Clock Select Register 0 Format
  182. CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT
  183. Buzzer Output Function Control Registers
  184. CHAPTER 14 A/D CONVERTER
  185. A/D Converter Configuration
  186. A/D Converter Block Diagram
  187. A/D Converter Control Registers
  188. A/D Converter Mode Register Format
  189. A/D Converter Input Select Register Format
  190. External Interrupt Mode Register 1 Format
  191. A/D Converter Operations
  192. A/D Converter Basic Operation
  193. Input voltage and conversion results
  194. A/D converter operating mode
  195. A/D Conversion by Software Start
  196. A/D Converter Cautions
  197. Connection of Analog Input Pin
  198. A/D Conversion End Interrupt Request Generation Timing
  199. CHAPTER 15 D/A CONVERTER
  200. D/A Converter Configuration
  201. D/A Converter Control Registers
  202. Operations of D/A Converter
  203. Cautions Related to D/A Converter
  204. CHAPTER 16 SERIAL INTERFACE CHANNEL 0 ( PD78058F SUBSERIES)
  205. Serial Interface Channel 0 Functions
  206. Serial Bus Interface (SBI) System Configuration Example
  207. Serial Interface Channel 0 Configuration
  208. Serial Interface Channel 0 Block Diagram
  209. Serial Interface Channel 0 Control Registers
  210. Timer Clock Select Register 3 Format
  211. Serial Operating Mode Register 0 Format
  212. Serial Bus Interface Control Register Format
  213. Interrupt Timing Specify Register Format
  214. Serial Interface Channel 0 Operations
  215. wire serial I/O mode operation
  216. Wire Serial I/O Mode Timings
  217. Circuit of Switching in Transfer Bit Order
  218. SBI mode operation
  219. SBI Transfer Timings
  220. Bus Release Signal
  221. Addresses
  222. Commands
  223. Acknowledge Signal
  224. BUSY and READY Signals
  225. RELT, CMDT, RELD, and CMDD Operations (Master)
  226. ACKT Operation
  227. ACKE Operations
  228. ACKD Operations
  229. Various Signals in SBI Mode
  230. Pin Configuration
  231. Address Transmission from Master Device to Slave Device (WUP = 1)
  232. Command Transmission from Master Device to Slave Device
  233. Data Transmission from Master Device to Slave Device
  234. Data Transmission from Slave Device to Master Device
  235. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
  236. RELT and CMDT Operations
  237. SCK0/P27 pin output manipulation
  238. CHAPTER 17 SERIAL INTERFACE CHANNEL 0 ( PD78058FY SUBSERIES)
  239. Serial Interface Channel 0 Interrupt Request Signal Generation
  240. Operation stop mode
  241. Start Condition
  242. Stop Condition
  243. Wait Signal
  244. Data Transmission from Master to Slave (Both Master and Slave Selected 9-Clock Wait)
  245. Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait)
  246. Start Condition Output
  247. Slave Wait Release (Transmission)
  248. Slave Wait Release (Reception)
  249. SCK0/SCL/P27 pin output manipulation
  250. Logic Circuit of SCL Signal
  251. CHAPTER 18 SERIAL INTERFACE CHANNEL 1
  252. Serial Interface Channel 1 Configuration
  253. Serial Interface Channel 1 Block Diagram
  254. Serial Interface Channel 1 Control Registers
  255. Serial Operating Mode Register 1 Format
  256. Automatic Data Transmit/Receive Control Register Format
  257. Automatic Data Transmit/Receive Interval Specify Register Format
  258. Serial Interface Channel 1 Operations
  259. wire serial I/O mode operation with automatic transmit/receive function
  260. Basic Transmission/Reception Mode Operation Timings
  261. Basic Transmission/Reception Mode Flowchart
  262. Basic Transmission Mode Operation Timings
  263. Basic Transmission Mode Flowchart
  264. Repeat Transmission Mode Operation Timing
  265. Repeat Transmission Mode Flowchart
  266. Automatic Transmission/Reception Suspension and Restart
  267. System Configuration When the Busy Control Option Is Used
  268. Operation Timings When Using Busy Control Option (BUSY0 = 0)
  269. Busy Signal and Wait Cancel (When BUSY0 = 0)
  270. Operation Timings When Using Busy & Strobe Control Option (BUSY0 = 0)
  271. Automatic Transmit/Receive Interval Time
  272. Operation Timing with Automatic Data Transmit/Receive Function Performed by Internal Clock
  273. Interval Timing Through CPU Processing (When the External Clock Is Operating)
  274. CHAPTER 19 SERIAL INTERFACE CHANNEL 2
  275. Serial Interface Channel 2 Configuration
  276. Serial Interface Channel 2 Block Diagram
  277. Baud Rate Generator Block Diagram
  278. Serial Interface Channel 2 Control Registers
  279. Asynchronous Serial Interface Mode Register Format
  280. Serial Interface Channel 2 Operating Mode Settings
  281. Asynchronous Serial Interface Status Register Format
  282. Baud Rate Generator Control Register Format
  283. Relationship Between Main System Clock and Baud Rate
  284. Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
  285. Serial Interface Channel 2 Operation
  286. Asynchronous serial interface (UART) mode
  287. Asynchronous Serial Interface Transmit/Receive Data Format
  288. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
  289. Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
  290. Receive Error Timing
  291. Receive Buffer Register (RXB) Status and Receive Completion Interrupt Request (INTSR Generation When Receiving Is Terminated
  292. wire serial I/O mode
  293. Wire Serial I/O Mode Timing
  294. Restrictions on using UART mode
  295. Period that Reading Receive Buffer Register Is Prohibited
  296. CHAPTER 20 REAL-TIME OUTPUT PORT
  297. Real-Time Output Port Configuration
  298. Real-time Output Buffer Register Configuration
  299. Real-Time Output Port Control Registers
  300. Real-time Output Port Control Register Format
  301. CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
  302. Interrupt Sources and Configuration
  303. Basic Configuration of Interrupt Function
  304. Interrupt Function Control Registers
  305. Interrupt Request Flag Register Format
  306. Interrupt Mask Flag Register Format
  307. Priority Specify Flag Register Format
  308. Noise Elimination Circuit Input/Output Timing (During Rising Edge Detection)
  309. Program Status Word Format
  310. Interrupt Servicing Operations
  311. Flowchart from the Time a Non-maskable Interrupt Request Is Generated Until It Is Received
  312. Non-Maskable Interrupt Request Acknowledge Operation
  313. Maskable Interrupt request reception
  314. Interrupt Request Acknowledge Processing Algorithm
  315. Interrupt Request Acknowledge Timing (Minimum Time)
  316. Software interrupt request acknowledge operation
  317. Interrupt Request Enabled for Multiple Interrupt During Interrupt Servicing
  318. Multiple Interrupt Example
  319. Interrupt request reserve
  320. Test Functions
  321. Format of Interrupt Request Flag Register 1L
  322. Test input signal acknowledge operation
  323. CHAPTER 22 EXTERNAL DEVICE EXPANSION FUNCTION
  324. Memory Map When Using External Device Expansion Function
  325. External Device Expansion Function Control Register
  326. Memory Size Switching Register Format
  327. External Device Expansion Function Timing
  328. Instruction Fetch from External Memory
  329. External Memory Read Timing
  330. External Memory Write Timing
  331. External Memory Read Modify Write Timing
  332. CHAPTER 23 STANDBY FUNCTION
  333. Standby function control register
  334. Standby Function Operations
  335. HALT Mode Clear upon Interrupt Request Generation
  336. HALT Mode Release by RESET Input
  337. STOP mode
  338. STOP Mode Release by Interrupt Request Generation
  339. Release by STOP Mode RESET Input
  340. CHAPTER 24 RESET FUNCTION
  341. Timing of Reset Input by RESET Input
  342. Hardware Status After Reset
  343. CHAPTER 25 ROM CORRECTION
  344. Correction Address Registers 0 and 1 Format
  345. ROM Correction Control Registers
  346. ROM Correction Application
  347. Initialization Routine
  348. ROM Correction Operation
  349. ROM Correction Example
  350. Program Execution Flow
  351. Program Transition Diagram (When Two Places Are Corrected)
  352. Cautions on ROM Correction
  353. CHAPTER 26 PD78P058F, 78P058FY
  354. Memory Size Switching Register
  355. Internal Expansion RAM Size Switching Register
  356. PROM Programming
  357. PROM write procedure
  358. Page Program Mode Timing
  359. Byte Program Mode Flowchart
  360. Byte Program Mode Timing
  361. PROM read procedure
  362. Screening of One-Time PROM Versions
  363. CHAPTER 27 INSTRUCTION SET
  364. Legends Used in Operation List
  365. Description of "operation" column
  366. Operation List
  367. Instructions Listed by Addressing Type
  368. APPENDIX A DIFFERENCES AMONG PD78054, 78058F, AND 780058 SUBSERIES
  369. APPENDIX B DEVELOPMENT TOOLS
  370. B-1 Development Tool Configuration
  371. B.1 Language Processing Software
  372. B.2 PROM Programming Tool
  373. B.3 Debugging Tool
  374. B.3.2 Software
  375. B.5 Upgrading Former In-circuit Emulators for 78K/0 Series to IE-78001-R-A
  376. B-2 EV-9200GC-80 Drawings (For Reference Only)
  377. B-3 EV-9200GC-80 Footprints (For Reference Only)
  378. B-4 TGK-080SDW Drawings (For Reference) (unit: mm)
  379. APPENDIX C EMBEDDED SOFTWARE
  380. C.1 Real-time OS
  381. APPENDIX D REGISTER INDEX
  382. APPENDIX E REVISION HISTORY
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This manual is suitable for:
PD78056FPD78056FYPD78058FPD78058F(A)PD78058FYPD78058FY(A)PD78P058FPD78P058FY
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