488CHAPTER 21 INTERRUPT AND TEST FUNCTIONSAddressFF47H 00HAfterReset R/WR/W0011INTP0 Sampling Clock Selectionfxx /2 Nfxx /2 7fxx /2 5fxx /2 6SCS170SymbolSCS60504030201SCS10SCS00101SCS0 MCS = 1 MCS = 0fx /2 7(39.1 kHz)fx /2 5(156.3 kHz)fx /2 6(78.1 kHz)f x/2 8(19.5 kHz)fx/2 6(78.1 kHz)fx/2 7(39.1 kHz)Caution f XX /2 N is a clock to be supplied to the CPU and f XX /2 5 , f XX /2 6 and f XX /2 7 are clocks to be suppliedto the peripheral hardware. f XX /2 N stops in the HALT mode.Remarks 1. N : Value (N=0 to 4) at bits 0 to 2 (PCC0 to PCC2) of processor clock control register2. f XX : Main system clock frequency (f X or f X /2)3. f X : Main system clock oscillation frequency4. MCS : Bit 0 of oscillation mode selection register (OSMS)5. Values in parentheses when operated with f X = 5.0 MHz.(5) Sampling clock select register (SCS)This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote controlleddata reception is carried out using INTP0, digital noise is removed with sampling clocks.SCS is set with an 8-bit memory manipulation instruction.RESET input sets SCS to 00H.Figure 21-7. Sampling Clock Select Register Format
