381CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (μPD78058FY SUBSERIES)WritingFFHto SIO0SettingCSIIF0SettingACKD Serial Reception9 a 2 3A0 R ACK D7 D6 D5P27outputlatch 1SettingCSIIF0ACKoutput Serial TransmissionWritedatato SIO0P27outputlatch 0WaitreleaseSoftware OperationHardware OperationSCLSoftware OperationHardware OperationTransfer LineMaster Device OperationSlave Device Operation1SDA0(SDA1)(2) Slave wait release (slave transmission)Slave wait status is released by WREL flag (bit 2 of interrupt timing specify register (SINT)) setting orexecution of an serial I/O shift register 0 (SIO0) write instruction.If the slave sends data, the wait is immediately released by execution of an SIO0 write instruction and theclock rises without the start transmission bit being output in the data line. Therefore, as shown in Figure17-25, data should be transmitted by manipulating the P27 output latch through the program. At this time,control the low-level width ("a" in Figure 17-25) of the first serial clock at the timing used for setting theP27 output latch to 1 after execution of an SIO0 write instruction.In addition, if the acknowledge signal from the master is not output (if data transmission from the slave iscompleted), set 1 in the WREL flag of SINT and release the wait.For these timings, see Figure 17-23.Figure 17-25. Slave Wait Release (Transmission)
